On 3/10/20 5:08 AM, Rick Chen wrote: > Hi Sean > >> Where possible, I have tried to find compatible drivers based on the layout >> of registers. However, many devices remain untested. All untested devices >> have been left disabled, but some tentative properties (such as compatible >> strings, and clocks, interrupts, and resets properties) have been added. >> >> Signed-off-by: Sean Anderson <sean...@gmail.com> >> --- >> >> Changes in v6: >> - Remove spi, gpio, pinmux, wdt, and led bindings >> - Use consistent capitalization for hex digits >> >> Changes in v5: >> - Add more compatible strings >> - Add cache line size >> - Document CPUs as rocket cores >> - Flesh out the gpio devices >> - Add ports for audio and video devices >> - Add fpioa pinctrl support >> - Configure pins for MMC on SPI1 >> - Enable MMC >> - Fix a couple uart properties (Thanks laanwj) >> - Reorder ram now that relocation is handled with CONFIG_SYS defines >> - Enable WDT >> - Add pinctrl properties >> - Add gpio support >> - Add led support >> - Add assorted AV bindings >> - Add compatible strings for ram >> - Use GPIO-based CS for MMC >> - Limit SPI flash to 50 MHz >> >> Changes in v4: >> - Set regs sizes to full address range >> - Remove clock-frequency property from cpus >> - Add spi-max-frequency to spi devices from documentation >> - Add more compatible strings for each device >> - Add AI ram as a separate memory bank. Its clock is disabled on boot, and >> it cannot be accessed >> - Reorder memory banks so u-boot relocates higher, leaving more room to >> load boot images >> - Add designware ssi CTRL0 field shifts to spi devices >> - Don't enable the MMC slot >> - Update copyright >> - Lint >> >> Changes in v3: >> - Move this patch to the end of the series >> - Add a max frequency for spi3 >> - Remov unused compatible strings from spi-flash@0 >> - Add s and u to isa string >> - Fix mmu-type >> - Remove cache-line size since it is unused (in u-boot) and undocumented >> (upstream) >> - Add timer interrupts to clint0 >> - Round up various registers >> - Add riscv,max-priority to plic >> - Add apb* busses, since they have clocks which need to be enabled to >> access their devices >> - Change uart compatible strings to "snps,dw-apb-uart", since that appears >> to match their registers >> - Add compatible string for wdt* >> - Add system reset device under sysctl >> - Add reset device under sysctl >> >> Changes in v2: >> - Model changed to "Sipeed Maix Bit" to match file name >> - Value of stdout-path fixed >> - SD card slot compatible changed to "mmc-spi-slot" >> - "jedec,spi-nor" added to spi flash compatible list >> - Aliases for spi busses added >> - timebase-frequency divided by 50 to match timer speed >> - cpu-frequency renamed to clock-frequency >> - CPUX_intc restyled to cpuX_intc >> - "kendryte,k210-soc" added to soc compatible list for future-proofing >> - PLIC handle renamed to plic0 from pic0 >> - K210_RST_SOC removed from sysrst, due to not being located in the reset >> register >> - K210_RST_* numbers changed to match their bit offset within the reset >> register >> - gpio_controller restyled to gpio-controller >> - Added a second clock to the dma binding to match what the driver expects >> - Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to >> match the correct driver >> - Added a name to the spi clocks >> - Added reg-io-width property to spi bindings >> - Assigned a default parent to K210_CLK_SPI3 >> - Removed assigned clocks for ACLK and PLLs >> - Removed u-boot,dm-pre-reloc bindings >> >> arch/riscv/dts/Makefile | 1 + >> arch/riscv/dts/k210-maix-bit.dts | 47 ++ >> arch/riscv/dts/k210.dtsi | 599 ++++++++++++++++++++++++ >> include/dt-bindings/reset/k210-sysctl.h | 38 ++ > > It is not proper to mix them in one patch.
The bindings and the device trees? > > Thanks, > Rick > --Sean