Hi Marek,

> From: Marek Vasut <ma...@denx.de>
> Sent: mardi 31 mars 2020 02:49
> 
> Add PHY reset GPIO on AV96 ethernet PHY.
> 
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Patrick Delaunay <patrick.delau...@st.com>
> Cc: Patrice Chotard <patrice.chot...@st.com>
> ---
> V2: No change
> ---
>  arch/arm/dts/stm32mp157a-avenger96.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
> b/arch/arm/dts/stm32mp157a-avenger96.dts
> index fb8f0021b3..7a4b6e6a2c 100644
> --- a/arch/arm/dts/stm32mp157a-avenger96.dts
> +++ b/arch/arm/dts/stm32mp157a-avenger96.dts
> @@ -101,6 +101,7 @@
>       phy-mode = "rgmii";
>       max-speed = <1000>;
>       phy-handle = <&phy0>;
> +     phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;

This obsolete binding is (and won't be) supported for STM32MP15x variant of 
dwc_eth_qos driver.

I am currenty upstream the support in U-boot of the support of the final binding
aligned with Kernel one.

"net: dwc_eth_qos: implement reset-gpios for stm32"
http://patchwork.ozlabs.org/patch/1257377/

=> phy-handle and "reset-gpios" in sub node PHY

>       mdio0 {
>               #address-cells = <1>;
> --
> 2.25.1

Regards

Patrick

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