Hi Marek, > From: Marek Vasut <ma...@denx.de> > Sent: mardi 31 mars 2020 02:49 > > The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and > FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not > easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC > devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. > Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz > instead, which is easy to divide to 50MHz for optimal operation of both SD and > eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Patrick Delaunay <patrick.delau...@st.com> > Cc: Patrice Chotard <patrice.chot...@st.com> > --- > V2: Move this patch before the split of AV96 into SoM and carrier > ---
Reviewed-by: Patrick Delaunay <patrick.delau...@st.com> Thanks Patrick