This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese <s...@denx.de>
---
arch/mips/lib/cache.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..9e20b39608 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <cpu_func.h>
#include <asm/cacheops.h>
-#ifdef CONFIG_MIPS_L2_CACHE
+#ifdef CONFIG_MIPS_CM
#include <asm/cm.h>
#endif
#include <asm/io.h>
@@ -16,6 +16,17 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_MIPS_L2_CACHE) && !defined(CONFIG_MIPS_CM)
+/*
+ * Dummy implementation to avoid compile warning on platforms with L2
+ * cache but without CM
+ */
+static unsigned long mips_cm_l2_line_size(void)
+{
+ return 0;
+}
+#endif
+
static void probe_l2(void)
{
#ifdef CONFIG_MIPS_L2_CACHE
--
2.26.2
