From: Suneel Garapati <sgarap...@marvell.com>
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.
Signed-off-by: Suneel Garapati <sgarap...@marvell.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Bin Meng <bmeng...@gmail.com>
Signed-off-by: Stefan Roese <s...@denx.de>
---
Changes in v1:
- Change patch subject
- Enhance Kconfig help descrition
- Use if() instead of #if
drivers/pci/Kconfig | 10 ++++++++++
drivers/pci/pci-uclass.c | 9 ++++++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ff974e5d74..14c96dd108 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -43,6 +43,16 @@ config PCI_PNP
help
Enable PCI memory and I/O space resource allocation and assignment.
+config PCI_REGION_MULTI_ENTRY
+ bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
+ depends on PCI || DM_PCI
+ default n
+ help
+ Enable PCI memory regions to be of multiple entry. Multiple entry
+ here refers to allow more than one count of address ranges for MEMORY
+ region type. This helps to add support for SoC's like OcteonTX/TX2
+ where every peripheral is on the PCI bus.
+
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
default n
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index fa2436a0ef..061ac4e943 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -936,10 +936,13 @@ static void decode_regions(struct pci_controller *hose,
ofnode parent_node,
}
pos = -1;
- for (i = 0; i < hose->region_count; i++) {
- if (hose->regions[i].flags == type)
- pos = i;
+ if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == type)
+ pos = i;
+ }
}
+
if (pos == -1)
pos = hose->region_count++;
debug(" - type=%d, pos=%d\n", type, pos);
--
2.27.0
