Dear York Sun, In message <[email protected]> you wrote: > The memory test is performed after DDR initialization when U-boot stills runs > in flash and cache. Whole memory can be tested. It is mapped 2GB at a time > using a sliding TLB window. After the testing, DDR is remapped with up to 2GB > memory from the lowest address as normal. > > If memory test fails, DDR DIMM SPD and DDR controller registers are dumped. > > Signed-off-by: York Sun <[email protected]>
Please see previous comments about empty lines etc. to make to code more readable. Also, please add some comments to explain what you are actually doing. > +Memory testing options for mpc85xx > +================================== > +1. Memory test can be done one U-boot prompt comes up using mtest, or s/one/once/ ? > +2. Memory test can be done with Power-On-Self-Test function, activated at > compile time. > + > + In order to enable the POST memory test, CONFIG_POST needs to be > + defined in board configuraiton header file. By default, POST memory test > performs > + a fast test. A slow test can be enabled by changing the flag at compiling > time. > + To test memory bigger than 2GB, 36BIT support is needed. Memory is tested > within > + a 2GB window. TLBs are used to map the virtual 2GB window to physical > address > + so that all physical memory can be tested. Lines too long. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] A supercomputer is a machine that runs an endless loop in 2 seconds. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
