[PATCH v2 3/9] arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel

[Teresa Remmet]

This update includes eqos support and debug uart changes.

Synced with kernel commit
846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")

Signed-off-by: Teresa Remmet <t.rem...@phytec.de>
---
 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++++++++++++++++++---
 arch/arm/dts/imx8mp-phycore-som.dtsi        |  2 +-
 2 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts 
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
index 0e1a6d953389..984a6b9ded8d 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
@@ -16,7 +16,7 @@
                     "phytec,imx8mp-phycore-som", "fsl,imx8mp";
 
        chosen {
-               stdout-path = &uart2;
+               stdout-path = &uart1;
        };
 
        reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -33,9 +33,33 @@
        };
 };
 
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0x1>;
+                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+                       enet-phy-lane-no-swap;
+               };
+       };
+};
+
 &i2c2 {
        clock-frequency = <400000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c2>;
        pinctrl-1 = <&pinctrl_i2c2_gpio>;
        sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -71,9 +95,9 @@
 };
 
 /* debug console */
-&uart2 {
+&uart1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2>;
+       pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 
@@ -90,6 +114,26 @@
 };
 
 &iomuxc {
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                     
0x3
+                       MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                   
0x3
+                       MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0               
0x91
+                       MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1               
0x91
+                       MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2               
0x91
+                       MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3               
0x91
+                       
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x91
+                       MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL         
0x91
+                       MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0               
0x1f
+                       MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1               
0x1f
+                       MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2               
0x1f
+                       MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3               
0x1f
+                       MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL         
0x1f
+                       
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x1f
+                       MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20                      
0x10
+               >;
+       };
+
        pinctrl_i2c2: i2c2grp {
                fsl,pins = <
                        MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL         0x400001c3
@@ -110,10 +154,10 @@
                >;
        };
 
-       pinctrl_uart2: uart2grp {
+       pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
-                       MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x49
+                       MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x49
+                       MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x49
                >;
        };
 
diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi 
b/arch/arm/dts/imx8mp-phycore-som.dtsi
index 44a8c2337cee..f3965ec5b31d 100644
--- a/arch/arm/dts/imx8mp-phycore-som.dtsi
+++ b/arch/arm/dts/imx8mp-phycore-som.dtsi
@@ -67,7 +67,7 @@
 
 &i2c1 {
        clock-frequency = <400000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c1>;
        pinctrl-1 = <&pinctrl_i2c1_gpio>;
        sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-- 
2.25.1