On Thu, Oct 21, 2021 at 07:50:46AM -0400, Tom Rini wrote:
> On Thu, Oct 21, 2021 at 09:07:42AM +0200, Michael Walle wrote:
> > Hi,
> >
> > > LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
> > >
> > > Signed-off-by: Gaurav Jain <gaurav.j...@nxp.com>
> > > Reviewed-by: Priyanka Jain <priyanka.j...@nxp.com>
> > > ---
> > > [..]
> > >
> > > diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
> > > index 50f9b527cd..c2a156ea8e 100644
> > > --- a/arch/arm/dts/fsl-ls1028a.dtsi
> > > +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> > > @@ -2,7 +2,7 @@
> > > /*
> > > * NXP ls1028a SOC common device tree source
> > > *
> > > - * Copyright 2019-2020 NXP
> > > + * Copyright 2019-2021 NXP
> >
> > This will be removed again, because its not part of the kernel device tree.
> >
> > > *
> > > */
> > >
> > > @@ -123,6 +123,45 @@
> > > 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0
> > > 0x40000000>; /* non-prefetchable memory */
> > > };
> > >
> > > + crypto: crypto@8000000 {
> > > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> > > + fsl,sec-era = <10>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges = <0x0 0x00 0x8000000 0x100000>;
> > > + reg = <0x00 0x8000000 0x0 0x100000>;
> > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> > > + dma-coherent;
> > > +
> > > + sec_jr0: jr@10000 {
> > > + compatible = "fsl,sec-v5.0-job-ring",
> > > + "fsl,sec-v4.0-job-ring";
> > > + reg = <0x10000 0x10000>;
> > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + sec_jr1: jr@20000 {
> > > + compatible = "fsl,sec-v5.0-job-ring",
> > > + "fsl,sec-v4.0-job-ring";
> > > + reg = <0x20000 0x10000>;
> > > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + sec_jr2: jr@30000 {
> > > + compatible = "fsl,sec-v5.0-job-ring",
> > > + "fsl,sec-v4.0-job-ring";
> > > + reg = <0x30000 0x10000>;
> > > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + sec_jr3: jr@40000 {
> > > + compatible = "fsl,sec-v5.0-job-ring",
> > > + "fsl,sec-v4.0-job-ring";
> > > + reg = <0x40000 0x10000>;
> > > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > + };
> > > +
> >
> > While this one will collide with my DTB sync series [1]. I'd prefer
> > to have my series merged first because then this patch will be unnecessary
> > and I don't have to respin my series (yet again) because there were changes
> > in the device tree in the meantime.
> >
> > [1] https://lore.kernel.org/u-boot/20211013161427.612033-1-mich...@walle.cc/
>
> Very much agreed with what Michael is saying here.
Me too. Priyanka, could you please take a look at Michael's patches?
