All platforms today define CONFIG_SYS_DDR_RAW_TIMING, so drop the code
for this option being unset.
Cc: Qiang Zhao <qiang.z...@nxp.com>
Signed-off-by: Tom Rini <tr...@konsulko.com>
---
board/freescale/p1010rdb/ddr.c | 138 ---------------------------------
include/configs/P1010RDB.h | 37 ---------
2 files changed, 175 deletions(-)
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 2625195f81b1..b423ec8e218a 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -16,142 +16,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE 1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {607, 749, &ddr_cfg_regs_667},
- {0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
- struct cpu_type *cpu;
- phys_size_t ddr_size;
-
- cpu = gd->arch.cpu;
- /* P1014 and it's derivatives support max 16it DDR width */
- if (cpu->soc_ver == SVR_P1014)
- ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
- else
- ddr_size = CONFIG_SYS_DRAM_SIZE;
-
- return ddr_size;
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
- struct cpu_type *cpu;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-#endif
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- cpu = gd->arch.cpu;
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (cpu->soc_ver == SVR_P1014) {
- ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
- ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
- /* divide SA and EA by two and then mask the rest so we don't
- * write to reserved fields */
- ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) &
0x0fff0fff;
- }
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -232,5 +96,3 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index fbba1f053185..def21e55a611 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -114,43 +114,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* DDR3 Controller Settings */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/* settings for DDR3 at 667MT/s */
-#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
-#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
-#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
-#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
-
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
--
2.25.1
