adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh V <ane...@ti.com>
---
arch/arm/cpu/armv7/omap4/board.c | 25 ++++++++++++++++++++++++-
arch/arm/cpu/armv7/omap4/lowlevel_init.S | 17 +++++++++++++++++
arch/arm/include/asm/arch-omap4/omap4.h | 6 ++++++
arch/arm/include/asm/arch-omap4/sys_proto.h | 3 ++-
include/configs/omap4_panda.h | 6 +++---
include/configs/omap4_sdp4430.h | 6 +++---
6 files changed, 55 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index fcd29a7..09612e5 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -31,7 +31,8 @@
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
-
+#include <asm/armv7.h>
+#include <asm/pl310.h>
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -127,3 +128,25 @@ int arch_cpu_init(void)
set_muxconf_regs();
return 0;
}
+
+/*
+ * Outer cache related functions
+ */
+#ifndef CONFIG_SYS_NO_DCACHE
+void v7_setup_outer_cache_ops(void)
+{
+#ifndef CONFIG_L2_OFF
+ v7_outer_cache.enable = omap4_enable_pl310;
+ v7_outer_cache.disable = omap4_disable_pl310;
+ v7_outer_cache.flush_all = pl310_clean_inval_all;
+ v7_outer_cache.flush_range = pl310_clean_inval_range;
+ v7_outer_cache.inval_range = pl310_inval_range;
+ /*
+ * Do not setup v7_outer_cache.inval_all
+ * Not needed in OMAP4 because ROM code invalidates entire L2$ at
+ * bootup.
+ */
+ v7_outer_cache.inval_all = NULL;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa4..4beed53 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -29,6 +29,8 @@
#include <asm/arch/omap4.h>
.globl lowlevel_init
+.globl omap4_enable_pl310
+.globl omap4_disable_pl310
lowlevel_init:
/*
* Setup a temporary stack
@@ -45,3 +47,18 @@ lowlevel_init:
*/
bl s_init
pop {ip, pc}
+
+set_pl310_ctrl_reg:
+ PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ @ our registers
+ LDR r12, =0x102 @ Set PL310 control register - value in R0
+ SMC #0 @ call ROM Code API to set control register
+ POP {r4-r11, pc}
+
+omap4_enable_pl310:
+ MOV r0, #1
+ B set_pl310_ctrl_reg
+
+omap4_disable_pl310:
+ MOV r0, #0
+ B set_pl310_ctrl_reg
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h
b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..9c6ec6f 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -100,6 +100,12 @@
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+/* PL310 base */
+#define CONFIG_SYS_PL310_BASE 0x48242000
+
+/* PL310 associativity */
+#define OMAP44XX_PL310_ASSOCIATIVITY 16
+
#ifndef __ASSEMBLY__
struct s32ktimer {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4813e9e..79c373d 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,8 @@ struct omap_sysinfo {
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
-void invalidate_dcache(u32);
+void omap4_enable_pl310(void);
+void omap4_disable_pl310(void);
void set_muxconf_regs(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 2b03b0f..0ec306a 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -45,9 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
-
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
@@ -234,4 +231,7 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#ifndef CONFIG_L2_OFF
+#define CONFIG_SYS_USE_PL310 1
+#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index d288333..0e5840e 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -46,9 +46,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
-
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
@@ -239,4 +236,7 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#ifndef CONFIG_L2_OFF
+#define CONFIG_SYS_USE_PL310 1
+#endif
#endif /* __CONFIG_H */
--
1.7.0.4
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