Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang <yanhong.w...@starfivetech.com>
---
arch/riscv/dts/Makefile | 3 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 85 ++++++
.../jh7110-starfive-visionfive-2-v1.2a.dts | 12 +
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 85 ++++++
.../jh7110-starfive-visionfive-2-v1.3b.dts | 12 +
.../dts/jh7110-starfive-visionfive-2.dtsi | 253 ++++++++++++++++++
6 files changed, 449 insertions(+), 1 deletion(-)
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55767..79a58694f5 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644
index 0000000000..161468f3e9
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ u-boot,dm-spl;
+ };
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&mmc0 {
+ u-boot,dm-spl;
+};
+
+&mmc1 {
+ u-boot,dm-spl;
+};
+
+&qspi {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&sysgpio {
+ u-boot,dm-spl;
+};
+
+&mmc0_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+&sdcard1_pins {
+ u-boot,dm-spl;
+ sdcard1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins1 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins2 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins3 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins4 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins5 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644
index 0000000000..b9d26d7af7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644
index 0000000000..161468f3e9
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ u-boot,dm-spl;
+ };
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&mmc0 {
+ u-boot,dm-spl;
+};
+
+&mmc1 {
+ u-boot,dm-spl;
+};
+
+&qspi {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&sysgpio {
+ u-boot,dm-spl;
+};
+
+&mmc0_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+&sdcard1_pins {
+ u-boot,dm-spl;
+ sdcard1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins1 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins2 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins3 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins4 {
+ u-boot,dm-spl;
+ };
+
+ sdcard1-pins5 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644
index 0000000000..3b3b3453a1
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.3B";
+ compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
new file mode 100644
index 0000000000..e669c2a26a
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+/ {
+ aliases {
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x2 0x0>;
+ };
+};
+
+&S7_0 {
+ status = "okay";
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&sysgpio {
+ status = "okay";
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE,
GPI_SYS_UART0_RX)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins1 {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD,
GPI_SYS_SDIO1_CMD)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins2 {
+ pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0,
GPI_SYS_SDIO1_DATA0)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins3 {
+ pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1,
GPI_SYS_SDIO1_DATA1)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins4 {
+ pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2,
GPI_SYS_SDIO1_DATA2)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins5 {
+ pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3,
GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&mmc0 {
+ compatible = "snps,dw-mshc";
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+
+};
+
+&mmc1 {
+ compatible = "snps,dw-mshc";
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ no-sdio;
+ no-mmc;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&uart0 {
+ reg-offset = <0>;
+ current-speed = <115200>;
+ clock-frequency = <24000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&qspi {
+ spi-max-frequency = <250000000>;
+ status = "okay";
+
+ nor-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ spi-max-frequency = <100000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+ };
+};
+
+&syscrg {
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+ <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+ <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
+ <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
+&aoncrg {
+ assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
+ assigned-clock-parents = <&osc>;
+ assigned-clock-rates = <0>;
+};
--
2.17.1
