[PATCH v1 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board

[Yanhong Wang]

The StarFive VisionFive2 board include 1.2A and 1.3B version.

v1.3B uses motorcomm YT8531(rgmii-id phy) x2, phy clock need delay and
inverse configurations.

v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs phy clock
delay configurations.

v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and
tx to external clock sources.

Signed-off-by: Yanhong Wang <yanhong.w...@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2-v1.2a.dts    | 13 +++++++
 .../jh7110-starfive-visionfive-2-v1.3b.dts    | 27 +++++++++++++++
 .../dts/jh7110-starfive-visionfive-2.dtsi     | 34 +++++++++++++++++++
 3 files changed, 74 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
index b9d26d7af7..918e77220a 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -10,3 +10,16 @@
        model = "StarFive VisionFive 2 v1.2A";
        compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
 };
+
+&gmac1 {
+       phy-mode = "rmii";
+       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
+                         <&syscrg JH7110_SYSCLK_GMAC1_RX>;
+       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
+                                <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+&phy0 {
+       rx-internal-delay-ps = <1900>;
+       tx-internal-delay-ps = <1350>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
index 3b3b3453a1..0fcd6ab80f 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -10,3 +10,30 @@
        model = "StarFive VisionFive 2 v1.3B";
        compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
 };
+
+&gmac0 {
+       starfive,tx-use-rgmii-clk;
+       assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+       assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+&gmac1 {
+       starfive,tx-use-rgmii-clk;
+       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
+       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+&phy0 {
+       motorcomm,tx-clk-adj-enabled;
+       motorcomm,tx-clk-100-inverted;
+       motorcomm,tx-clk-1000-inverted;
+       rx-internal-delay-ps = <1900>;
+       tx-internal-delay-ps = <1500>;
+};
+
+&phy1 {
+       motorcomm,tx-clk-adj-enabled;
+       motorcomm,tx-clk-100-inverted;
+       rx-internal-delay-ps = <0>;
+       tx-internal-delay-ps = <0>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
                i2c2 = &i2c2;
                i2c5 = &i2c5;
                i2c6 = &i2c6;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
        };
 
        chosen {
@@ -317,3 +319,35 @@
        assigned-clock-parents = <&osc>;
        assigned-clock-rates = <0>;
 };
+
+&gmac0 {
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
+       };
+};
+
+&gmac1 {
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+
+               phy1: ethernet-phy@1 {
+                       reg = <0>;
+               };
+       };
+};
-- 
2.17.1