On Thu, Mar 16, 2023 at 10:53:29AM +0800, Yanhong Wang wrote: > Add initial device tree for the JH7110 RISC-V SoC. > > Signed-off-by: Yanhong Wang <yanhong.w...@starfivetech.com> > Tested-by: Conor Dooley <conor.doo...@microchip.com>
> + S7_0: cpu@0 { > + compatible = "sifive,s7", "riscv"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <8192>; > + d-tlb-sets = <1>; > + d-tlb-size = <40>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <16384>; > + i-tlb-sets = <1>; > + i-tlb-size = <40>; > + mmu-type = "riscv,sv39"; Copy-pasting from my identical post on linux-riscv: Jess pointed out on IRC that this S7 entry looks wrong as it is claiming that the S7 has an mmu. I didn't go looking back in the history of u74-mc core complex manuals, but the latest version does not show an mmu for the S7. Cheers, Conor. > + next-level-cache = <&ccache>; > + riscv,isa = "rv64imac_zba_zbb"; > + tlb-split; > + status = "disabled"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + };
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