On Wednesday 08 March 2023 13:48:33 Minda Chen wrote:
> From: Mason Huo <mason....@starfivetech.com>
>
> Enable and add pinctrl configuration for PCIe host controller.
> Also add JH7110 stg syscon configuration.
>
> Signed-off-by: Mason Huo <mason....@starfivetech.com>
> Signed-off-by: Minda Chen <minda.c...@starfivetech.com>
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 99 +++++++++++++++++++
> arch/riscv/dts/jh7110.dtsi | 75 ++++++++++++++
> 2 files changed, 174 insertions(+)
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e669c2a26a..995f842a6b 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -178,6 +178,87 @@
> slew-rate = <0>;
> };
> };
> +
> + pcie0_perst_default: pcie0_perst_default {
> + perst-pins {
> + pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE,
> GPI_NONE)>;
> + drive-strength = <2>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> + pcie0_perst_active: pcie0_perst_active {
> + perst-pins {
> + pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE,
> GPI_NONE)>;
> + drive-strength = <2>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
...
> +&pcie0 {
> + pinctrl-names = "perst-default", "perst-active", "wake-default",
> "clkreq-default";
> + pinctrl-0 = <&pcie0_perst_default>;
> + pinctrl-1 = <&pcie0_perst_active>;
> + pinctrl-2 = <&pcie0_wake_default>;
> + pinctrl-3 = <&pcie0_clkreq_default>;
> + status = "disabled";
> +};
This is not correct declaration of PERST# signal. You should define in
&pcie0 node "reset-gpios" property with plain gpio definition with
active state.
"reset-gpios" is standard PCIe property for controlling PERST# signal
over GPIO. Look for example into drivers/pci/pci-aardvark.c and
arch/arm/dts/armada-3720-espressobin.dtsi files how it is used.
