This moves the PCIe controller definitions under /soc and adopts
the same bindings (fsl,ls1088a-pcie) as Linux. Previously,
the format was different between the two versions.
Signed-off-by: Mathew McBride <m...@traverse.com.au>
---
arch/arm/dts/fsl-ls1088a.dtsi | 154 +++++++++++++++++++++++-----------
1 file changed, 106 insertions(+), 48 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 05da798380..71d652c818 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -81,6 +81,112 @@
status = "disabled";
};
+ pcie1: pcie@3400000 {
+ compatible = "fsl,ls1088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller
registers */
+ <0x20 0x00000000 0x0 0x00002000>; /*
configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer
interrupt */
+ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <256>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0
0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 0 110
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 0 111
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 0 112
IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ };
+
+ pcie_ep1: pcie-ep@3400000 {
+ compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x20 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <24>;
+ num-ob-windows = <256>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
+ pcie2: pcie@3500000 {
+ compatible = "fsl,ls1088a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller
registers */
+ <0x28 0x00000000 0x0 0x00002000>; /*
configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer
interrupt */
+ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <6>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0
0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 0 115
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 0 116
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 0 117
IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ };
+
+ pcie_ep2: pcie-ep@3500000 {
+ compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x28 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ status = "disabled";
+ };
+
+ pcie3: pcie@3600000 {
+ compatible = "fsl,ls1088a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller
registers */
+ <0x30 0x00000000 0x0 0x00002000>; /*
configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer
interrupt */
+ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <6>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0
0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 0 120
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 0 121
IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 0 122
IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ };
+
+ pcie_ep3: pcie-ep@3600000 {
+ compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x30 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
@@ -335,54 +441,6 @@
};
};
- pcie1: pcie@3400000 {
- compatible = "fsl,ls-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
- 0x00 0x03480000 0x0 0x80000 /* lut registers */
- 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
- 0x20 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0
0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
- };
-
- pcie2: pcie@3500000 {
- compatible = "fsl,ls-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
- 0x00 0x03580000 0x0 0x80000 /* lut registers */
- 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
- 0x28 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0
0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
- };
-
- pcie3: pcie@3600000 {
- compatible = "fsl,ls-pcie", "snps,dw-pcie";
- reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
- 0x00 0x03680000 0x0 0x80000 /* lut registers */
- 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
- 0x30 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <8>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0
0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
- };
-
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
--
2.30.1
