From: Peng Fan <peng....@nxp.com>
i.MX8MN/P has Cortex-M7, i.MX93 has Cortex-M33, so use "M4" is a bit
misleading, so update the name of the macro
Signed-off-by: faqiang.zhu <faqiang....@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +-
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +-
arch/arm/mach-imx/imx9/imx_bootaux.c | 6 +++---
arch/arm/mach-imx/imx_bootaux.c | 24 +++++++++++-----------
board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +-
board/kontron/sl-mx8mm/spl.c | 2 +-
board/technexion/pico-imx8mq/pico-imx8mq.c | 2 +-
board/technexion/pico-imx8mq/spl.c | 2 +-
include/imx_sip.h | 6 +++---
10 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 6e2fc82a0e4..8632eddb530 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -13,7 +13,7 @@
#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
-#define M4_BOOTROM_BASE_ADDR 0x007E0000
+#define MCU_BOOTROM_BASE_ADDR 0x007E0000
#define GPIO1_BASE_ADDR 0X30200000
#define GPIO2_BASE_ADDR 0x30210000
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 72944af18a4..8fd3dd2df3a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -23,7 +23,7 @@
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR 0x007F8000
+#define MCU_BOOTROM_BASE_ADDR 0x007F8000
#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index c863cd9da36..6f5ae5173c0 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -18,7 +18,7 @@
#define GIC400_ARB_END_ADDR 0x31007FFF
#define APBH_DMA_ARB_BASE_ADDR 0x33000000
#define APBH_DMA_ARB_END_ADDR 0x33007FFF
-#define M4_BOOTROM_BASE_ADDR 0x00180000
+#define MCU_BOOTROM_BASE_ADDR 0x00180000
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
index 256e6fa1c54..6afb59e0515 100644
--- a/arch/arm/mach-imx/imx9/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
{
struct arm_smccc_res res;
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
0, 0, 0, 0, &res);
return res.a0;
@@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)
printf("## Stopping auxiliary core\n");
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
0, 0, 0, 0, &res);
return 0;
@@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0,
0, 0, 0, 0, &res);
return 0;
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 888c53d6901..2b97aae3a23 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -124,15 +124,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
stack, pc);
- /* Set the stack and pc to M4 bootROM */
- writel(stack, M4_BOOTROM_BASE_ADDR);
- writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+ /* Set the stack and pc to MCU bootROM */
+ writel(stack, MCU_BOOTROM_BASE_ADDR);
+ writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
flush_dcache_all();
- /* Enable M4 */
+ /* Enable MCU */
if (IS_ENABLED(CONFIG_IMX8M)) {
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0,
0, NULL);
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0,
0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@@ -147,7 +147,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
unsigned int val;
if (IS_ENABLED(CONFIG_IMX8M)) {
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0,
0, 0, &res);
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0,
0, 0, &res);
return res.a0;
}
@@ -164,13 +164,13 @@ int arch_auxiliary_core_check_up(u32 core_id)
* the reset vector at the head for the image, with SP and PC
* as the first two words.
*
- * Per the cortex-M reference manual, the reset vector of M4 needs
- * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
- * of that vector. So to boot M4, the A core must build the M4's reset
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
* vector with getting the PC and SP from image and filling them to
- * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
- * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
- * accessing the M4 TCMUL.
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
*/
static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c
b/board/kontron/sl-mx8mm/sl-mx8mm.c
index 250195694ba..f0c95d17b1a 100644
--- a/board/kontron/sl-mx8mm/sl-mx8mm.c
+++ b/board/kontron/sl-mx8mm/sl-mx8mm.c
@@ -37,7 +37,7 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);
int board_phys_sdram_size(phys_size_t *size)
{
- u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+ u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 4) {
*size = 0x100000000;
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 3a919d0a9c3..b49373442a2 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -106,7 +106,7 @@ static void spl_dram_init(void)
}
gd->ram_size = size;
- writel(size, M4_BOOTROM_BASE_ADDR);
+ writel(size, MCU_BOOTROM_BASE_ADDR);
}
int do_board_detect(void)
diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c
b/board/technexion/pico-imx8mq/pico-imx8mq.c
index 951e3e1985b..2be3206f78a 100644
--- a/board/technexion/pico-imx8mq/pico-imx8mq.c
+++ b/board/technexion/pico-imx8mq/pico-imx8mq.c
@@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_phys_sdram_size(phys_size_t *size)
{
- int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+ int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 0x4) {
*size = 0x100000000;
diff --git a/board/technexion/pico-imx8mq/spl.c
b/board/technexion/pico-imx8mq/spl.c
index 8b853a914e8..2afb4d37608 100644
--- a/board/technexion/pico-imx8mq/spl.c
+++ b/board/technexion/pico-imx8mq/spl.c
@@ -89,7 +89,7 @@ static void spl_dram_init(void)
printf("%s: LPDDR4 %d GiB\n", __func__, size);
ddr_init(dram_timing);
- writel(size, M4_BOOTROM_BASE_ADDR);
+ writel(size, MCU_BOOTROM_BASE_ADDR);
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 1b873f231be..54317f20427 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -13,8 +13,8 @@
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
#define IMX_SIP_SRC 0xC2000005
-#define IMX_SIP_SRC_M4_START 0x00
-#define IMX_SIP_SRC_M4_STARTED 0x01
-#define IMX_SIP_SRC_M4_STOP 0x02
+#define IMX_SIP_SRC_MCU_START 0x00
+#define IMX_SIP_SRC_MCU_STARTED 0x01
+#define IMX_SIP_SRC_MCU_STOP 0x02
#endif
--
2.40.0
