This is for new platform enablement for agilex5.
Add in new configuration that needed to boot new platform.

Signed-off-by: Jit Loon Lim <jit.loon....@intel.com>
---
 arch/arm/mach-socfpga/Kconfig                 |  55 +++++
 configs/socfpga_agilex5_defconfig             |   2 +
 configs/socfpga_agilex5_legacy_defconfig      |   2 +
 include/configs/socfpga_agilex5_socdk.h       |  12 +
 include/configs/socfpga_soc64_common.h        | 214 +++++++++++++++++-
 include/dt-bindings/clock/agilex5-clock.h     |  71 ++++++
 include/dt-bindings/reset/altr,rst-mgr-agx5.h |  82 +++++++
 7 files changed, 428 insertions(+), 10 deletions(-)
 create mode 100644 include/configs/socfpga_agilex5_socdk.h
 create mode 100644 include/dt-bindings/clock/agilex5-clock.h
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 562c3796ec..a35928ef47 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -3,6 +3,10 @@ if ARCH_SOCFPGA
 config ERR_PTR_OFFSET
        default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
 
+config MEM_RESERVE_SECURE
+       int
+       default 0
+
 config NR_DRAM_BANKS
        default 1
 
@@ -33,6 +37,37 @@ config SPL_STACK_R_ADDR
 config SPL_SYS_MALLOC_F_LEN
        default 0x800 if TARGET_SOCFPGA_GEN5
 
+config SYS_CACHELINE_SIZE
+       default 64
+
+config SYS_INIT_RAM_ADDR
+       bool
+       default 0xFFE00000 if TARGET_SOCFPGA_AGILEX
+       default 0x0 if TARGET_SOCFPGA_AGILEX5
+       default 0xFFE00000 if TARGET_SOCFPGA_N5X
+       default 0xFFE00000 if TARGET_SOCFPGA_STRATIX10
+
+config SYS_INIT_RAM_SIZE
+       bool
+       default 0x40000 if TARGET_SOCFPGA_AGILEX
+       default 0x80000 if TARGET_SOCFPGA_AGILEX5
+       default 0x40000 if TARGET_SOCFPGA_N5X
+       default 0x40000 if TARGET_SOCFPGA_STRATIX10
+
+config SYS_MAX_NAND_DEVICE
+       default 1
+
+config SYS_NAND_ONFI_DETECTION
+       default 1
+
+config SYS_NAND_U_BOOT_SIZE
+       int
+       default 1048576
+
+config SYS_NAND_U_BOOT_DST
+       bool
+       default CONFIG_TEXT_BASE if TARGET_SOCFPGA_SOC64
+
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
        default 0xa2
 
@@ -40,6 +75,16 @@ config SYS_MALLOC_F_LEN
        default 0x2000 if TARGET_SOCFPGA_ARRIA10
        default 0x2000 if TARGET_SOCFPGA_GEN5
 
+config SYS_NS16550_MEM32
+       default y if TARGET_SOCFPGA_SOC64
+
+config SYS_SDRAM_BASE
+       bool
+       default 0x0 if TARGET_SOCFPGA_AGILEX
+       default 0x80000000 if TARGET_SOCFPGA_AGILEX5
+       default 0x0 if TARGET_SOCFPGA_N5X
+       default 0x0 if TARGET_SOCFPGA_STRATIX10
+
 config TEXT_BASE
        default 0x01000040 if TARGET_SOCFPGA_ARRIA10
        default 0x01000040 if TARGET_SOCFPGA_GEN5
@@ -59,29 +104,35 @@ config TARGET_SOCFPGA_AGILEX
        select ARMV8_SET_SMPEN
        select BINMAN if SPL_ATF
        select CLK
+       select CONFIG_BOOTFILE if SPL_ATF
        select FPGA_INTEL_SDM_MAILBOX
        select GICV2
        select NCORE_CACHE
        select SPL_CLK if SPL
+       select SYS_SDRAM_BASE
        select TARGET_SOCFPGA_SOC64
 
 config TARGET_SOCFPGA_AGILEX5
        bool
        select BINMAN if SPL_ATF
        select CLK
+       select CONFIG_BOOTFILE if SPL_ATF
        select FPGA_INTEL_SDM_MAILBOX
        select GICV3
        select NCORE_CACHE
        select SPL_CLK if SPL
+       select SYS_SDRAM_BASE
        select TARGET_SOCFPGA_SOC64
 
 config TARGET_SOCFPGA_AGILEX5_EMU
        bool "Enable build that bootable only on Agilex5 Emulator"
+       select TARGET_SOCFPGA_AGILEX5
        help
         This is to use for Agilex5 Emulator.
 
 config TARGET_SOCFPGA_AGILEX5_SIMICS
        bool "Enable build that bootable only on Agilex5 Simics platform"
+       select TARGET_SOCFPGA_AGILEX5
        help
         This is to use for Agilex5 Simics.
 
@@ -127,10 +178,12 @@ config TARGET_SOCFPGA_N5X
        select ARMV8_SET_SMPEN
        select BINMAN if SPL_ATF
        select CLK
+       select CONFIG_BOOTFILE if SPL_ATF
        select FPGA_INTEL_SDM_MAILBOX
        select NCORE_CACHE
        select SPL_ALTERA_SDRAM
        select SPL_CLK if SPL
+       select SYS_SDRAM_BASE
        select TARGET_SOCFPGA_SOC64
 
 config TARGET_SOCFPGA_N5X_SOCDK
@@ -145,7 +198,9 @@ config TARGET_SOCFPGA_STRATIX10
        select ARMV8_MULTIENTRY
        select ARMV8_SET_SMPEN
        select BINMAN if SPL_ATF
+       select CONFIG_BOOTFILE if SPL_ATF
        select FPGA_INTEL_SDM_MAILBOX
+       select SYS_SDRAM_BASE
        select TARGET_SOCFPGA_SOC64
 
 choice
diff --git a/configs/socfpga_agilex5_defconfig 
b/configs/socfpga_agilex5_defconfig
index 6a90fa0b27..8e5c7e6f70 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -50,6 +50,8 @@ CONFIG_CMD_FAT=y
 CONFIG_DOS_PARTITION=y
 CONFIG_SPL_DOS_PARTITION=y
 CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
diff --git a/configs/socfpga_agilex5_legacy_defconfig 
b/configs/socfpga_agilex5_legacy_defconfig
index cede11c880..054f785b6e 100644
--- a/configs/socfpga_agilex5_legacy_defconfig
+++ b/configs/socfpga_agilex5_legacy_defconfig
@@ -45,6 +45,8 @@ CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_CMD_FAT=y
 CONFIG_DOS_PARTITION=y
 CONFIG_SPL_DOS_PARTITION=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_NAND_LOCK_UNLOCK=y
diff --git a/include/configs/socfpga_agilex5_socdk.h 
b/include/configs/socfpga_agilex5_socdk.h
new file mode 100644
index 0000000000..ad2b5632d1
--- /dev/null
+++ b/include/configs/socfpga_agilex5_socdk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX5_H__
+#define __CONFIG_SOCFGPA_AGILEX5_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */
diff --git a/include/configs/socfpga_soc64_common.h 
b/include/configs/socfpga_soc64_common.h
index 66ecb168a0..04466dc8ac 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2023 Intel Corporation <www.intel.com>
  *
  */
 
@@ -18,25 +18,185 @@
 #define CPU_RELEASE_ADDR               0xFFD12210
 
 /*
- * U-Boot console configurations
+ * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to
+ * store its VBAR_EL3 value. Other slave CPUs will read from this
+ * location and update their VBAR_EL3 respectively
+ */
+#define VBAR_EL3_BASE_ADDR             0xFFD12218
+/*
+ * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR
+ * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3.
+ */
+#define L2_RESET_DONE_REG              0xFFD12218
+
+/*
+ * sysmgr.boot_scratch_cold8 bit 19 (1bit) will be used to check whether CPU0
+ * is being powered off/on from kernel
  */
+#define BOOT_SCRATCH_COLD8             0xFFD12220
 
-/* Extend size of kernel image for uncompression */
+/* Magic word to indicate L2 reset is completed */
+#define L2_RESET_DONE_STATUS           0x1228E5E7
+
+/*
+ * U-Boot console configurations
+ */
 
 /*
  * U-Boot run time memory configurations
  */
-#define CFG_SYS_INIT_RAM_ADDR  0xFFE00000
-#define CFG_SYS_INIT_RAM_SIZE  0x40000
 
 /*
  * U-Boot environment configurations
  */
 
+/*
+ * NAND support
+ */
+
 /*
  * Environment variable
  */
+
+#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)
+#if IS_ENABLED(CONFIG_CMD_MMC)
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if IS_ENABLED(CONFIG_CMD_SF)
+#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+#define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+       "bootcmd_qspi=sf probe && " \
+       "ubi part root && ubi readvol ${scriptaddr} script && " \
+       "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+       "source ${scriptaddr}; " \
+       "echo QSPI: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+       "qspi "
+
+#if IS_ENABLED(CONFIG_CMD_NAND)
+# define BOOT_TARGET_DEVICES_NAND(func)        func(NAND, nand, na)
+#else
+# define BOOT_TARGET_DEVICES_NAND(func)
+#endif
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+       "bootcmd_nand=ubi part root && " \
+       "ubi readvol ${scriptaddr} script && " \
+       "echo NAND: Trying to boot script at ${scriptaddr} && " \
+       "source ${scriptaddr}; " \
+       "echo NAND: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+       "nand "
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS)
+#define BOOT_TARGET_DEVICES(func) \
+       BOOT_TARGET_DEVICES_MMC(func) \
+       BOOT_TARGET_DEVICES_QSPI(func)
+#else
+#define BOOT_TARGET_DEVICES(func) \
+       BOOT_TARGET_DEVICES_MMC(func) \
+       BOOT_TARGET_DEVICES_QSPI(func) \
+       BOOT_TARGET_DEVICES_NAND(func)
+#endif
+
+#include <config_distro_bootcmd.h>
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+
+#define CFG_EXTRA_ENV_SETTINGS \
+       "kernel_addr_r=0x82000000\0" \
+       "fdt_addr_r=0x86000000\0" \
+       "qspiscriptaddr=0x02110000\0" \
+       "scriptsize=0x00010000\0" \
+       "qspibootimageaddr=0x02120000\0" \
+       "bootimagesize=0x03200000\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "bootfile=" CONFIG_BOOTFILE "\0" \
+       "mmcroot=/dev/mmcblk0p2\0" \
+       "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+       "linux_qspi_enable=if sf probe; then " \
+               "echo Enabling QSPI at Linux DTB...;" \
+               "fdt addr ${fdt_addr}; fdt resize;" \
+               "fdt set /soc/spi@108d2000 status okay;" \
+               "if fdt set /clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " else fdt set /clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
+       "scriptaddr=0x81000000\0" \
+       "scriptfile=boot.scr\0" \
+       "nandroot=ubi0:rootfs\0" \
+       "socfpga_legacy_reset_compat=1\0" \
+       "rsu_status=rsu dtb; rsu display_dcmf_version; "\
+               "rsu display_dcmf_status; rsu display_max_retry\0" \
+       "smc_fid_rd=0xC2000007\0" \
+       "smc_fid_wr=0xC2000008\0" \
+       "smc_fid_upd=0xC2000009\0 " \
+       BOOTENV
+
+#else
+
+#define CFG_EXTRA_ENV_SETTINGS \
+       "kernel_addr_r=0x2000000\0" \
+       "fdt_addr_r=0x6000000\0" \
+       "qspiscriptaddr=0x02110000\0" \
+       "scriptsize=0x00010000\0" \
+       "qspibootimageaddr=0x02120000\0" \
+       "bootimagesize=0x03200000\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "bootfile=" CONFIG_BOOTFILE "\0" \
+       "mmcroot=/dev/mmcblk0p2\0" \
+       "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+       "linux_qspi_enable=if sf probe; then " \
+               "echo Enabling QSPI at Linux DTB...;" \
+               "fdt addr ${fdt_addr}; fdt resize;" \
+               "fdt set /soc/spi@ff8d2000 status okay;" \
+               "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " else fdt set /clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
+       "scriptaddr=0x05FF0000\0" \
+       "scriptfile=boot.scr\0" \
+       "nandroot=ubi0:rootfs\0" \
+       "socfpga_legacy_reset_compat=1\0" \
+       "rsu_status=rsu dtb; rsu display_dcmf_version; "\
+               "rsu display_dcmf_status; rsu display_max_retry\0" \
+       "smc_fid_rd=0xC2000007\0" \
+       "smc_fid_wr=0xC2000008\0" \
+       "smc_fid_upd=0xC2000009\0 " \
+       BOOTENV
+#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/
+
+#else
+
 #define CFG_EXTRA_ENV_SETTINGS \
+       "kernel_comp_addr_r=0x9000000\0" \
+       "kernel_comp_size=0x01000000\0" \
+       "qspibootimageaddr=0x020E0000\0" \
+       "qspifdtaddr=0x020D0000\0" \
+       "bootimagesize=0x01F00000\0" \
+       "fdtimagesize=0x00010000\0" \
+       "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \
+               "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \
+       "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \
+               "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \
+       "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} 
${bootimagesize}\0" \
+       "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \
+               "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \
        "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "bootfile=" CONFIG_BOOTFILE "\0" \
        "fdt_addr=8000000\0" \
@@ -53,30 +213,64 @@
                "bootm ${loadaddr}\0" \
        "mmcfitload=mmc rescan;" \
                "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+       "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
        "linux_qspi_enable=if sf probe; then " \
                "echo Enabling QSPI at Linux DTB...;" \
                "fdt addr ${fdt_addr}; fdt resize;" \
                "fdt set /soc/spi@ff8d2000 status okay;" \
-               "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
-               " ${qspi_clock}; fi; \0" \
+               "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+               " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+               " else fdt set /clocks/qspi-clk clock-frequency" \
+               " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
        "scriptaddr=0x02100000\0" \
        "scriptfile=u-boot.scr\0" \
        "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
-                  "then source ${scriptaddr}; fi\0" \
-       "socfpga_legacy_reset_compat=1\0"
+                  "then source ${scriptaddr}:script; fi\0" \
+       "nandroot=ubi0:rootfs\0" \
+       "nandload=ubi part root; ubi readvol ${loadaddr} kernel; ubi readvol 
${fdt_addr} dtb\0" \
+       "nandboot=setenv bootargs " CONFIG_BOOTARGS \
+                       " root=${nandroot} rw rootwait rootfstype=ubifs 
ubi.mtd=1; " \
+                       "booti ${loadaddr} - ${fdt_addr}\0" \
+       "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \
+                       " root=${nandroot} rw rootwait rootfstype=ubifs 
ubi.mtd=1; " \
+                       "bootm ${loadaddr}\0" \
+       "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \
+       "socfpga_legacy_reset_compat=1\0" \
+       "rsu_status=rsu dtb; rsu display_dcmf_version; "\
+               "rsu display_dcmf_status; rsu display_max_retry\0" \
+       "smc_fid_rd=0xC2000007\0" \
+       "smc_fid_wr=0xC2000008\0" \
+       "smc_fid_upd=0xC2000009\0 "
+#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/
 
 /*
  * External memory configurations
  */
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define PHYS_SDRAM_1                   0x80000000
+#define PHYS_SDRAM_1_SIZE              (1 * 1024 * 1024 * 1024)
+#else
 #define PHYS_SDRAM_1                   0x0
 #define PHYS_SDRAM_1_SIZE              (1 * 1024 * 1024 * 1024)
-#define CFG_SYS_SDRAM_BASE             0
+#endif
 
 /*
  * Serial / UART configurations
  */
 #define CFG_SYS_NS16550_CLK            100000000
 
+/*
+ * Timer & watchdog configurations
+ */
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS)
+#define COUNTER_FREQUENCY              80000000
+#else
+#define COUNTER_FREQUENCY              400000000
+#endif
+
 /*
  * SDMMC configurations
  */
diff --git a/include/dt-bindings/clock/agilex5-clock.h 
b/include/dt-bindings/clock/agilex5-clock.h
new file mode 100644
index 0000000000..2691084653
--- /dev/null
+++ b/include/dt-bindings/clock/agilex5-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019-2022, Intel Corporation
+ */
+
+#ifndef __AGILEX5_CLOCK_H
+#define __AGILEX5_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX5_OSC1                   0
+#define AGILEX5_CB_INTOSC_HS_DIV2_CLK  1
+#define AGILEX5_CB_INTOSC_LS_CLK               2
+#define AGILEX5_L4_SYS_FREE_CLK                3
+#define AGILEX5_F2S_FREE_CLK           4
+
+/* PLL clocks */
+#define AGILEX5_MAIN_PLL_CLK           5
+#define AGILEX5_MAIN_PLL_C0_CLK                6
+#define AGILEX5_MAIN_PLL_C1_CLK                7
+#define AGILEX5_MAIN_PLL_C2_CLK                8
+#define AGILEX5_MAIN_PLL_C3_CLK                9
+#define AGILEX5_PERIPH_PLL_CLK         10
+#define AGILEX5_PERIPH_PLL_C0_CLK      11
+#define AGILEX5_PERIPH_PLL_C1_CLK      12
+#define AGILEX5_PERIPH_PLL_C2_CLK      13
+#define AGILEX5_PERIPH_PLL_C3_CLK      14
+#define AGILEX5_MPU_FREE_CLK           15
+#define AGILEX5_MPU_CCU_CLK            16
+#define AGILEX5_BOOT_CLK                       17
+
+/* fixed factor clocks */
+#define AGILEX5_L3_MAIN_FREE_CLK               18
+#define AGILEX5_NOC_FREE_CLK           19
+#define AGILEX5_S2F_USR0_CLK           20
+#define AGILEX5_NOC_CLK                        21
+#define AGILEX5_EMAC_A_FREE_CLK                22
+#define AGILEX5_EMAC_B_FREE_CLK                23
+#define AGILEX5_EMAC_PTP_FREE_CLK      24
+#define AGILEX5_GPIO_DB_FREE_CLK               25
+#define AGILEX5_SDMMC_FREE_CLK         26
+#define AGILEX5_S2F_USER0_FREE_CLK     27
+#define AGILEX5_S2F_USER1_FREE_CLK     28
+#define AGILEX5_PSI_REF_FREE_CLK               29
+
+/* Gate clocks */
+#define AGILEX5_MPU_CLK                        30
+#define AGILEX5_MPU_PERIPH_CLK         31
+#define AGILEX5_L4_MAIN_CLK            32
+#define AGILEX5_L4_MP_CLK              33
+#define AGILEX5_L4_SP_CLK              34
+#define AGILEX5_CS_AT_CLK              35
+#define AGILEX5_CS_TRACE_CLK           36
+#define AGILEX5_CS_PDBG_CLK            37
+#define AGILEX5_CS_TIMER_CLK           38
+#define AGILEX5_S2F_USER0_CLK          39
+#define AGILEX5_EMAC0_CLK              40
+#define AGILEX5_EMAC1_CLK              41
+#define AGILEX5_EMAC2_CLK              42
+#define AGILEX5_EMAC_PTP_CLK           43
+#define AGILEX5_GPIO_DB_CLK            44
+#define AGILEX5_NAND_CLK                       45
+#define AGILEX5_PSI_REF_CLK            46
+#define AGILEX5_S2F_USER1_CLK          47
+#define AGILEX5_SDMMC_CLK              48
+#define AGILEX5_SPI_M_CLK              49
+#define AGILEX5_USB_CLK                        50
+#define AGILEX5_NAND_X_CLK             51
+#define AGILEX5_NAND_ECC_CLK           52
+#define AGILEX5_NUM_CLKS                       53
+
+#endif /* __AGILEX5_CLOCK_H */
diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h 
b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
new file mode 100644
index 0000000000..601093eaba
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2023 Intel Corporation. All rights reserved
+ * Copyright (C) 2016 Altera Corporation. All rights reserved
+ * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+
+/* PER0MODRST */
+#define EMAC0_RESET            0
+#define EMAC1_RESET            1
+#define EMAC2_RESET            2
+#define USB0_RESET             3
+#define USB1_RESET             4
+#define NAND_RESET             5
+#define COMBOPHY_RESET         6
+#define SDMMC_RESET            7
+#define EMAC0_OCP_RESET                8
+#define EMAC1_OCP_RESET                9
+#define EMAC2_OCP_RESET                10
+#define USB0_OCP_RESET         11
+#define USB1_OCP_RESET         12
+#define NAND_OCP_RESET         13
+/* 14 is empty */
+#define SDMMC_OCP_RESET                15
+#define DMA_RESET              16
+#define SPIM0_RESET            17
+#define SPIM1_RESET            18
+#define SPIS0_RESET            19
+#define SPIS1_RESET            20
+#define DMA_OCP_RESET          21
+#define EMAC_PTP_RESET         22
+/* 23 is empty*/
+#define DMAIF0_RESET           24
+#define DMAIF1_RESET           25
+#define DMAIF2_RESET           26
+#define DMAIF3_RESET           27
+#define DMAIF4_RESET           28
+#define DMAIF5_RESET           29
+#define DMAIF6_RESET           30
+#define DMAIF7_RESET           31
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET                32
+#define WATCHDOG1_RESET                33
+#define WATCHDOG2_RESET                34
+#define WATCHDOG3_RESET                35
+#define L4SYSTIMER0_RESET      36
+#define L4SYSTIMER1_RESET      37
+#define SPTIMER0_RESET         38
+#define SPTIMER1_RESET         39
+#define I2C0_RESET             40
+#define I2C1_RESET             41
+#define I2C2_RESET             42
+#define I2C3_RESET             43
+#define I2C4_RESET             44
+#define I3C0_RESET             45
+#define I3C1_RESET             46
+/* 47 is empty */
+#define UART0_RESET            48
+#define UART1_RESET            49
+/* 50-55 is empty */
+#define GPIO0_RESET            56
+#define GPIO1_RESET            57
+#define WATCHDOG4_RESET                58
+/* 59-63 is empty */
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET         64
+#define LWHPS2FPGA_RESET       65
+#define FPGA2SOC_RESET         66
+#define F2SSDRAM_RESET         67
+/* 68-69 is empty */
+#define DDRSCH_RESET           70
+/* 71-95 is empty */
+
+/* DBGMODRST */
+#define DBG_RESET              192
+
+#endif
-- 
2.26.2

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