On Feb 8, 2011, at 2:51 PM, Haiying Wang wrote: > P1021 has some QE pins which need to be set in pmuxcr register before using QE > functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth > mode. > QE9 and QE12 are set for MII management. QE12 needs to be released after MII > access because QE12 pin is muxed with LBCTL signal. > > Signed-off-by: Haiying Wang <haiying.w...@freescale.com> > --- > v3: change resetting micrel phy via bcsr to board specific. > arch/powerpc/cpu/mpc85xx/speed.c | 4 ++ > arch/powerpc/include/asm/immap_85xx.h | 13 ++++++++ > board/freescale/p1021mds/p1021mds.c | 51 +++++++++++++++++++++++++++++++++ > drivers/qe/uec.c | 41 +++++++++++++++++++++++++- > include/configs/P1021MDS.h | 44 ++++++++++++++++++++++++++++ > 5 files changed, 152 insertions(+), 1 deletions(-)
still want to see QE related changes in their own patch, I'll post a version that merges part of this and part of 2/4 into one patch. - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
