From: Damon Ding <damon.d...@rock-chips.com> Fix use of wrong clk selection for CLK_PWM1 on RK3568.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Damon Ding <damon.d...@rock-chips.com> Signed-off-by: Jonas Karlman <jo...@kwiboo.se> --- drivers/clk/rockchip/clk_rk3568.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 0df82f597152..e8e4d20e532c 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1142,7 +1142,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) switch (clk_id) { case CLK_PWM1: - sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; break; case CLK_PWM2: sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; -- 2.41.0