Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---
drivers/pinctrl/renesas/pfc-r8a77970.c | 40 +++++++++++++++++---------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c
b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 04f03452336..1cc6fa4f3fc 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -21,10 +21,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn,
SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -172,7 +173,7 @@
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2)
F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_3_0 FM(DU_DG4) F_(0, 0)
F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0)
#define IP1_7_4 FM(DU_DG5) F_(0, 0)
F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0)
-#define IP1_11_8 FM(DU_DG6) F_(0, 0)
F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0)
F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0)
F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0)
F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0)
F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
@@ -2344,7 +2345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -2359,26 +2360,37 @@ static const struct pinmux_ioctrl_reg
pinmux_ioctrl_regs[] = {
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
- if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7;
- return -EINVAL;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.40.1
