On 10/4/23 11:18, Paul Barker wrote:
[...]
+static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x03F00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E00000UL,
What's this part about ?
This is copied from the RCar Gen3 memory map.
I suspected as much. Please recheck the memory map instead of copy-paste
and make sure it is really matching the hardware.
+ .phys = 0x47E00000UL,
+ .size = 0xF8200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rzg2l_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define debug_memmap(i, map) \
+ debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx,
attrs=0x%llx\n", \
+ i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
+
+void enable_caches(void)
+{
+ unsigned int bank, i = 0;
+ u64 start, size;
+
+ /* Create map for register access */
+ rzg2l_mem_map[i].virt = 0x0ULL;
+ rzg2l_mem_map[i].phys = 0x0ULL;
+ rzg2l_mem_map[i].size = 0x40000000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ /* Generate entries for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x48000000) {
+ /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
+ rzg2l_mem_map[i].virt = 0x40000000ULL;
+ rzg2l_mem_map[i].phys = 0x40000000ULL;
+ rzg2l_mem_map[i].size = 0x03F00000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ start = 0x47E00000ULL;
+ size += 0x00200000ULL;
+ }
+
+ rzg2l_mem_map[i].virt = start;
+ rzg2l_mem_map[i].phys = start;
+ rzg2l_mem_map[i].size = size;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+ }
Is this somehow copied from R-Car ? Can this be deduplicated ?
This is based on the R-Car memory map. We discussed internally whether
to modify memmap-gen3.c or create a separate memmap-rzg2l.c and decided
that it was safer not to change the known working code for R-Car systems.
To merge the two, we'll need to add a few if(IS_ENABLED(CONFIG_RZG2L))
conditionals to memmap-gen3.c. I'm happy to do that if that's the
approach you'd prefer.
I suspect if you really align the memmap with your hardware, there will
be even more differences. All right, lets stick with this setup for now.
