On 06:33-20231005, Nishanth Menon wrote: > On 11:56-20231004, Reid Tonking wrote: > > Sync j7200 dts with Linux 6.6-rc1 > [..] > > diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts > > b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts > > index e62f9218e8..9469dca39f 100644 > > --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts > > +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts > > @@ -1,13 +1,14 @@ > > // SPDX-License-Identifier: GPL-2.0 > > /* > > - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > > + * Copyright (C) 2020-2023 Texas Instruments Incorporated - > > https://www.ti.com/ > > */ > > > > /dts-v1/; > > > > -#include "k3-j7200-som-p0.dtsi" > > +#include "k3-j7200-common-proc-board.dts" > > #include "k3-j7200-ddr-evm-lp4-2666.dtsi" > > #include "k3-j721e-ddr.dtsi" > > +#include "k3-j7200-common-proc-board-u-boot.dtsi" > > > > / { > > aliases { > > @@ -15,17 +16,6 @@ > > remoteproc1 = &a72_0; > > }; > > > > - chosen { > > - stdout-path = &main_uart0; > > - tick-timer = &timer1; > > - firmware-loader = &fs_loader0; > > - }; > > - > > - fs_loader0: fs_loader@0 { > > - bootph-all; > > - compatible = "u-boot,fs-loader"; > > - }; > > - > > a72_0: a72@0 { > > compatible = "ti,am654-rproc"; > > reg = <0x0 0x00a90000 0x0 0x10>; > > @@ -39,21 +29,17 @@ > > ti,sci = <&dmsc>; > > ti,sci-proc-id = <32>; > > ti,sci-host-id = <10>; > > - bootph-pre-ram; > > - }; > > - > > - clk_200mhz: dummy_clock_200mhz { > > - compatible = "fixed-clock"; > > - #clock-cells = <0>; > > - clock-frequency = <200000000>; > > - bootph-pre-ram; > > + bootph-all; > > Here and else where in the r5 file: why switch from pre-ram to bootph-all > ? dont we need these prior to ddr initialization? >
Due to the change in how booth-pre-ram works [0], bootph-pre-ram alone no longer works. U-boot docs Pre-Relocation Support section says some-ram can be used for u-boot prior to reloc, but not spl. So like Massimo mentioned in the linked discussion, some-ram + pre-ram can work, as well as -all. Outside of affecting the TPL phase, I'm not sure I know of a difference in regards to how it affects pre-ddr. [0]: https://lore.kernel.org/u-boot/capnjgz3mgwx8t0a0sofpher_xd77pe3hte9dnye1rubveb9...@mail.gmail.com/ > [...] > > -- > Regards, > Nishanth Menon > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 > 849D 1736 249D
