Hi Jonas,
On 2/2/24 12:10, Quentin Schulz wrote:
Hi Jonas,
On 2/1/24 21:06, Jonas Karlman wrote:
Hi Quentin,
On 2024-02-01 13:40, Quentin Schulz wrote:
Hi Jonas,
On 2/1/24 11:51, Jonas Karlman wrote:
Hi Quentin,
On 2024-02-01 11:18, Quentin Schulz wrote:
Hi Jonas,
On 1/27/24 12:15, Jonas Karlman wrote:
Hi Eugen,
On 2024-01-27 04:48, Eugen Hristev wrote:
Hi Jonas,
On 1/27/24 01:26, Jonas Karlman wrote:
Writing to eMMC using DDR52 mode does not work reliably or at
all on
RK356x and RK3588 boards.
This is related to the old issue I encountered last year with mmc
write?
Yes, I think it is.
I did some testing on RK3566/RK3568/RK3588S/RK3588 boards with
different
eMMC modules with following result:
Read seem to work with all enabled modes:
RK3566: MMC legacy, MMC High Speed (26MHz), MMC High Speed (52MHz),
MMC DDR52 (52MHz) and HS200 (200MHz)
RK3568/RK3588S/RK3588: all above + HS400 (200MHz) and HS400ES
(200MHz)
However, write had issues with some of the modes:
MMC DDR52 (52MHz): all RK35xx
HS400/HS400ES: only on RK3568 after changing hs400_txclk_tapnum to 8
HS200 seem to be the most stable write speed that worked on all SoCs.
So, dropping MMC DDR52 (52MHz) and enable use of HS200 (200MHz)
seem to
be the best option to get speedy and working read and write eMMC.
1) we have this enabled on RK3588 Jaguar in upstream Linux... I may
have
improperly tested it then, would you mind sharing how you tested this
mode on RK3588 so I can reproduce this and fix it on our product if
we're impacted? I assume because we have HS200/HS400/HS400-ES enabled,
DDR52 would never be used? (our eMMC is soldered and support the
former
modes).
OK so just tested this in Linux kernel 5.10 from Rockchip and v6.6.7
with some patches for rk3588 (and the jaguar dts). I ran the following
tests:
$ fio --filename=/dev/mmcblk0 --rw=read --direct=1 --name=fioBench
--bs=1M --ioengine=libaio --cmdprio_percentage=100 --output-format=json
--allow_file_create=0 --time_based=1 --runtime=60 --ioscheduler=none
$ fio --filename=/dev/mmcblk0 --rw=write --direct=1 --name=fioBench
--bs=1M --ioengine=libaio --cmdprio_percentage=100 --output-format=json
--allow_file_create=0 --time_based=1 --runtime=60 --ioscheduler=none;
It worked in HS200, HS400, HS400ES without any issue. It worked in
high-speed.
It was a bit "difficult" to get the kernel to switch to DDR52 because
even with the property gone from the DTB it would detect the card as
HS200. I had to comment out
https://elixir.bootlin.com/linux/latest/source/drivers/mmc/host/sdhci.c#L4558
to force it into DDR52 (or what I assume to be DDR52 :) the kernel
prints: "mmc0: new DDR MMC card at address 0001" ). It failed reads in
that mode so didn't even test writes, but not sure if it's a fair test
with the aforementioned line commented out. I see it's also there in the
SDHCI implementation in U-Boot, so maybe it's just that mmc rescan 4
doesn't actually make much sense to test since I would assume it would
just detect it as HS200 even without the DT property? (or maybe
something really is missing there in the SDHCI logic?).
I couldn't quickly find out how to put the eMMC into non high-speed mode
so gave up on that.
Cheers,
Quentin
