Add another mux option for QSPI pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Patrice Chotard <patrice.chot...@foss.st.com>
Cc: Patrick Delaunay <patrick.delau...@foss.st.com>
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 51 +++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index cf070fbd7f7..77a222903de 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -305,6 +305,57 @@
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0
*/
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1
*/
+ <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2
*/
+ <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3
*/
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /*
QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /*
QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, ANALOG)>, /*
QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, ANALOG)>; /*
QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /*
QSPI_BK1_NCS */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
--
2.43.0
