On Wed, 08 Jan 2025 14:22:24 +0000, Caleb Connolly <[email protected]> wrote: > > This seems to cause crashes on a bunch of Qualcomm platforms. It's safer > to just update the live table and flush it.
You may want to provide a bit more information, because that's not much to go on, really. > > Signed-off-by: Caleb Connolly <[email protected]> > --- > arch/arm/cpu/armv8/cache_v8.c | 11 ++--------- > arch/arm/include/asm/system.h | 3 +-- > drivers/soc/qcom/cmd-db.c | 2 +- > 3 files changed, 4 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c > index e6be6359c5d9..43051d156122 100644 > --- a/arch/arm/cpu/armv8/cache_v8.c > +++ b/arch/arm/cpu/armv8/cache_v8.c > @@ -338,9 +338,9 @@ static void map_range(u64 virt, u64 phys, u64 size, int > level, > size -= next_size; > } > } > > -void mmu_map_region(phys_addr_t addr, u64 size, bool emergency) > +void mmu_map_region(phys_addr_t addr, u64 size) > { > u64 va_bits; > int level = 0; > u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; > @@ -350,19 +350,12 @@ void mmu_map_region(phys_addr_t addr, u64 size, bool > emergency) > get_tcr(NULL, &va_bits); > if (va_bits < 39) > level = 1; > > - if (emergency) > - map_range(addr, addr, size, level, > - (u64 *)gd->arch.tlb_emerg, attrs); > - > - /* Switch pagetables while we update the primary one */ > - __asm_switch_ttbr(gd->arch.tlb_emerg); > - > map_range(addr, addr, size, level, > (u64 *)gd->arch.tlb_addr, attrs); > > - __asm_switch_ttbr(gd->arch.tlb_addr); > + flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_size); Why would you invalidate anything when *mapping* something? By definition, if there was nothing mapped before, there is nothing to invalidate (hint: the architecture forbids negative caching). M. -- Without deviation from the norm, progress is not possible.
