Remove the separate topckgen-cg driver for handling clock gates in the topckgen address space. The devicetree bindings for this were not acceptable upstream because it was creating a separate clock controller using the same address space as the main topckgen clock controller. The gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt8365.c | 49 ++++++++++++--------------------------- 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index eaa5c2cf0dc..a28547a0cf8 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -500,18 +500,6 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; -static const struct mtk_clk_tree mt8365_topckgen_tree = { - .xtal_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_MFGPLL, - .muxes_offs = CLK_TOP_AXI_SEL, - .fclks = top_fixed_clks, - .fdivs = top_divs, - .muxes = top_muxes, - .num_fclks = ARRAY_SIZE(top_fixed_clks), - .num_fdivs = ARRAY_SIZE(top_divs), - .num_muxes = ARRAY_SIZE(top_muxes), -}; - /* topckgen cg */ static const struct mtk_gate_regs top0_cg_regs = { .set_ofs = 0, @@ -577,6 +565,21 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), }; +static const struct mtk_clk_tree mt8365_topckgen_tree = { + .xtal_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_MFGPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_AUD_I2S0_M, + .fclks = top_fixed_clks, + .fdivs = top_divs, + .muxes = top_muxes, + .gates = top_clk_gates, + .num_fclks = ARRAY_SIZE(top_fixed_clks), + .num_fdivs = ARRAY_SIZE(top_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_clk_gates), +}; + /* infracfg */ static const struct mtk_gate_regs ifr2_cg_regs = { .set_ofs = 0x80, @@ -725,13 +728,6 @@ static int mt8365_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8365_topckgen_tree); } -static int mt8365_topckgen_cg_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt8365_topckgen_tree, top_clk_gates, - ARRAY_SIZE(top_clk_gates), - CLK_TOP_AUD_I2S0_M); -} - static int mt8365_infracfg_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks, @@ -748,11 +744,6 @@ static const struct udevice_id mt8365_topckgen_compat[] = { { } }; -static const struct udevice_id mt8365_topckgen_cg_compat[] = { - { .compatible = "mediatek,mt8365-topckgen-cg", }, - { } -}; - static const struct udevice_id mt8365_infracfg_compat[] = { { .compatible = "mediatek,mt8365-infracfg", }, { } @@ -778,16 +769,6 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { - .name = "mt8365-topckgen-cg", - .id = UCLASS_CLK, - .of_match = mt8365_topckgen_cg_compat, - .probe = mt8365_topckgen_cg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - U_BOOT_DRIVER(mtk_clk_infracfg) = { .name = "mt8365-infracfg", .id = UCLASS_CLK, -- 2.43.0
