Use a ID map to add clocks for the missing CLK_TOP_CLK32K and CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a parent. CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted now since we can do that with the ID map as well. Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt8365.c | 151 +++++++++++++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index a28547a0cf8..6ba464097ae 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -75,6 +75,146 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = { }; /* topckgen */ + +/* + * The devicetree bindings missed a few clocks and can't be changed, so we need + * to provide a mapping to fix the omissions. + */ +static const int mt8365_topckgen_id_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + /* Fixed 32K oscillator is not available in devicetree definitions */ + [CLK_TOP_CLK32K] = 0, + [CLK_TOP_CLK_NULL] = 1, + [CLK_TOP_I2S0_BCK] = 2, + [CLK_TOP_DSI0_LNTC_DSICK] = 3, + [CLK_TOP_VPLL_DPIX] = 4, + [CLK_TOP_LVDSTX_CLKDIG_CTS] = 5, + /* FACTOR */ + [CLK_TOP_MFGPLL] = 6, + [CLK_TOP_SYSPLL_D2] = 7, + [CLK_TOP_SYSPLL1_D2] = 8, + [CLK_TOP_SYSPLL1_D4] = 9, + [CLK_TOP_SYSPLL1_D8] = 10, + [CLK_TOP_SYSPLL1_D16] = 11, + [CLK_TOP_SYSPLL_D3] = 12, + [CLK_TOP_SYSPLL2_D2] = 13, + [CLK_TOP_SYSPLL2_D4] = 14, + [CLK_TOP_SYSPLL2_D8] = 15, + [CLK_TOP_SYSPLL_D5] = 16, + [CLK_TOP_SYSPLL3_D2] = 17, + [CLK_TOP_SYSPLL3_D4] = 18, + [CLK_TOP_SYSPLL_D7] = 19, + [CLK_TOP_SYSPLL4_D2] = 20, + [CLK_TOP_SYSPLL4_D4] = 21, + /* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */ + [CLK_TOP_UNIVPLL_D2] = 22, + [CLK_TOP_UNIVPLL1_D2] = 23, + [CLK_TOP_UNIVPLL1_D4] = 24, + [CLK_TOP_UNIVPLL_D3] = 25, + [CLK_TOP_UNIVPLL2_D2] = 26, + [CLK_TOP_UNIVPLL2_D4] = 27, + [CLK_TOP_UNIVPLL2_D8] = 28, + [CLK_TOP_UNIVPLL2_D32] = 29, + [CLK_TOP_UNIVPLL_D5] = 30, + [CLK_TOP_UNIVPLL3_D2] = 31, + [CLK_TOP_UNIVPLL3_D4] = 32, + [CLK_TOP_MMPLL] = 33, + [CLK_TOP_MMPLL_D2] = 34, + [CLK_TOP_LVDSPLL_D2] = 35, + [CLK_TOP_LVDSPLL_D4] = 36, + [CLK_TOP_LVDSPLL_D8] = 37, + [CLK_TOP_LVDSPLL_D16] = 38, + [CLK_TOP_USB20_192M] = 39, + [CLK_TOP_USB20_192M_D4] = 40, + [CLK_TOP_USB20_192M_D8] = 41, + [CLK_TOP_USB20_192M_D16] = 42, + [CLK_TOP_USB20_192M_D32] = 43, + [CLK_TOP_APLL1] = 44, + [CLK_TOP_APLL1_D2] = 45, + [CLK_TOP_APLL1_D4] = 46, + [CLK_TOP_APLL1_D8] = 47, + [CLK_TOP_APLL2] = 48, + [CLK_TOP_APLL2_D2] = 49, + [CLK_TOP_APLL2_D4] = 50, + [CLK_TOP_APLL2_D8] = 51, + /* Fixed 26M oscillator is not available in devicetree definitions */ + [CLK_TOP_CLK26M] = 52, + [CLK_TOP_SYS_26M_D2] = 53, + [CLK_TOP_MSDCPLL] = 54, + [CLK_TOP_MSDCPLL_D2] = 55, + [CLK_TOP_DSPPLL] = 56, + [CLK_TOP_DSPPLL_D2] = 57, + [CLK_TOP_DSPPLL_D4] = 58, + [CLK_TOP_DSPPLL_D8] = 59, + [CLK_TOP_APUPLL] = 60, + [CLK_TOP_CLK26M_D52] = 61, + /* MUX */ + [CLK_TOP_AXI_SEL] = 62, + [CLK_TOP_MEM_SEL] = 63, + [CLK_TOP_MM_SEL] = 64, + [CLK_TOP_SCP_SEL] = 65, + [CLK_TOP_MFG_SEL] = 66, + [CLK_TOP_ATB_SEL] = 67, + [CLK_TOP_CAMTG_SEL] = 68, + [CLK_TOP_CAMTG1_SEL] = 69, + [CLK_TOP_UART_SEL] = 70, + [CLK_TOP_SPI_SEL] = 71, + [CLK_TOP_MSDC50_0_HC_SEL] = 72, + [CLK_TOP_MSDC2_2_HC_SEL] = 73, + [CLK_TOP_MSDC50_0_SEL] = 74, + [CLK_TOP_MSDC50_2_SEL] = 75, + [CLK_TOP_MSDC30_1_SEL] = 76, + [CLK_TOP_AUDIO_SEL] = 77, + [CLK_TOP_AUD_INTBUS_SEL] = 78, + [CLK_TOP_AUD_1_SEL] = 79, + [CLK_TOP_AUD_2_SEL] = 80, + [CLK_TOP_AUD_ENGEN1_SEL] = 81, + [CLK_TOP_AUD_ENGEN2_SEL] = 82, + [CLK_TOP_AUD_SPDIF_SEL] = 83, + [CLK_TOP_DISP_PWM_SEL] = 84, + [CLK_TOP_DXCC_SEL] = 85, + [CLK_TOP_SSUSB_SYS_SEL] = 86, + [CLK_TOP_SSUSB_XHCI_SEL] = 87, + [CLK_TOP_SPM_SEL] = 88, + [CLK_TOP_I2C_SEL] = 89, + [CLK_TOP_PWM_SEL] = 90, + [CLK_TOP_SENIF_SEL] = 91, + [CLK_TOP_AES_FDE_SEL] = 92, + [CLK_TOP_CAMTM_SEL] = 93, + [CLK_TOP_DPI0_SEL] = 94, + [CLK_TOP_DPI1_SEL] = 95, + [CLK_TOP_DSP_SEL] = 96, + [CLK_TOP_NFI2X_SEL] = 97, + [CLK_TOP_NFIECC_SEL] = 98, + [CLK_TOP_ECC_SEL] = 99, + [CLK_TOP_ETH_SEL] = 100, + [CLK_TOP_GCPU_SEL] = 101, + [CLK_TOP_GCPU_CPM_SEL] = 102, + [CLK_TOP_APU_SEL] = 103, + [CLK_TOP_APU_IF_SEL] = 104, + /* GATE */ + [CLK_TOP_AUD_I2S0_M] = 105, + [CLK_TOP_AUD_I2S1_M] = 106, + [CLK_TOP_AUD_I2S2_M] = 107, + [CLK_TOP_AUD_I2S3_M] = 108, + [CLK_TOP_AUD_TDMOUT_M] = 109, + [CLK_TOP_AUD_TDMOUT_B] = 110, + [CLK_TOP_AUD_TDMIN_M] = 111, + [CLK_TOP_AUD_TDMIN_B] = 112, + [CLK_TOP_AUD_SPDIF_M] = 113, + [CLK_TOP_USB20_48M_EN] = 114, + [CLK_TOP_UNIVPLL_48M_EN] = 115, + [CLK_TOP_LVDSTX_CLKDIG_EN] = 116, + [CLK_TOP_VPLL_DPIX_EN] = 117, + [CLK_TOP_SSUSB_TOP_CK_EN] = 118, + [CLK_TOP_SSUSB_PHY_CK_EN] = 119, + [CLK_TOP_CONN_32K] = 120, + [CLK_TOP_CONN_26M] = 121, + [CLK_TOP_DSP_32K] = 122, + [CLK_TOP_DSP_26M] = 123, +}; + #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) @@ -82,6 +222,7 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = { FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK0(CLK_TOP_CLK32K, 32000), FIXED_CLK0(CLK_TOP_CLK_NULL, 0), FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), @@ -115,7 +256,6 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), - PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIV_EN, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), @@ -146,6 +286,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), + PLL_FACTOR2(CLK_TOP_CLK26M, "clk26m_ck", CLK_XTAL, 1, 1), PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), @@ -567,9 +708,11 @@ static const struct mtk_gate top_clk_gates[] = { static const struct mtk_clk_tree mt8365_topckgen_tree = { .xtal_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_MFGPLL, - .muxes_offs = CLK_TOP_AXI_SEL, - .gates_offs = CLK_TOP_AUD_I2S0_M, + .id_offs_map = mt8365_topckgen_id_map, + .id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map), + .fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL], + .muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL], + .gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M], .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes, -- 2.43.0
