The TS233 is a 2 bay NAS similar to the TS433. Architecture-wise it really seems to be the same minus the additional PCIe connected components the TS433 has.
So it just uses two of the SoCs SATA ports and the SoC's gigabit ethernet. Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patch.msgid.link/[email protected] [ upstream commit: ce0b84e766ad7b2ec5d2ac7840675f223640f3e3 ] (cherry picked from commit be3ad0fe4738a324213dcf63efaccfd00fca9918) --- .../src/arm64/rockchip/rk3568-qnap-ts233.dts | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts new file mode 100644 index 00000000000..f16d1c62879 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Heiko Stuebner <[email protected]> + */ + +/dts-v1/; + +#include "rk3568-qnap-tsx33.dtsi" + +/ { + model = "Qnap TS-233-2G NAS System 2-Bay"; + compatible = "qnap,ts233", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + }; +}; + +/* connected to sata2 */ +&combphy2 { + status = "okay"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; +}; + +&i2c1 { + /* eeprom for vital-product-data on the backplane */ + eeprom@56 { + compatible = "giantec,gt24c04a", "atmel,24c04"; + reg = <0x56>; + label = "VPD_BP"; + num-addresses = <2>; + pagesize = <16>; + read-only; + }; +}; + +&leds { + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + label = "hdd2:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_led_pin>; + }; +}; + +&mcu { + compatible = "qnap,ts233-mcu"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + hdd2_led_pin: hdd2-led-pin { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +/* connected to usb_host1_ehci/ohci */ +&usb2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* connected to usb_host0_ehci/ohci */ +&usb2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* right port backside */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* left port backside */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; -- 2.47.2
