Re: [PATCH] arm: spl: Fix DTB offset after binman symbol table

[Tom Rini]

On Fri, Jan 23, 2026 at 01:19:07PM -0300, Fabio Estevam wrote:

> From: Fabio Estevam <feste...@nabladev.com>
> 
> When CONFIG_SPL_SEPARATE_BSS is disabled, SPL expects the embedded device
> tree to start exactly at __bss_end. This address is fixed by the linker
> script and SPL probes this location directly for FDT_MAGIC at runtime.
> 
> Commit 8b0ebe054bb3 ("arm: Update linker scripts to ensure appended device
> tree is aligned") modified the linker layout such that the
> .binman_sym_table section may end at a non-word-aligned offset. Since no
> alignment is enforced at the end of this section, the DTB is written a
> few bytes past __bss_end in u-boot-spl.bin, even though the __bss_end
> symbol itself remains correctly aligned and unchanged.
> 
> As a result, SPL reads zeroes at __bss_end instead of FDT_MAGIC, leading
> to a "Missing DTB" failure, while the DTB is actually present at
> __bss_end + 4.
> 
> Align the end of the .binman_sym_table section to 8 bytes so that the DTB
> is placed exactly at __bss_end as expected.
> 
> This fixes SPL boot regressions observed on Rockchip RV1103 and RV1126.
> 
> Fixes: 8b0ebe054bb3 ("arm: Update linker scripts to ensure appended device 
> tree is aligned")
> Signed-off-by: Fabio Estevam <feste...@nabladev.com>
> ---
>  arch/arm/cpu/u-boot-spl.lds | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
> index d780a5060774..fc2b7fcb969f 100644
> --- a/arch/arm/cpu/u-boot-spl.lds
> +++ b/arch/arm/cpu/u-boot-spl.lds
> @@ -40,6 +40,7 @@ SECTIONS
>       .binman_sym_table : {
>               __binman_sym_start = .;
>               KEEP(*(SORT(.binman_sym*)));
> +             . = ALIGN(8);
>               __binman_sym_end = .;
>       }
>  

I've been talking with Ilias for the last few hours. This still isn't
right, it just happens to work in some cases, but not others. What's
going on is that while we always have u-boot-nodtb.bin 8-byte aligned
because while the BSS itself may end 8 byte aligned, we actually care
about the size of the BSS being 8 byte aligned. Can you please try:

diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index d780a5060774..dae8a1ec665b 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -58,6 +58,7 @@ SECTIONS
        _end = .;
 
        .bss __rel_dyn_start (OVERLAY) : {
+               . = ALIGN(8);
                __bss_start = .;
                *(.bss*)
                 . = ALIGN(8);

And see if it works at run time? hexdump'ing looks good. If so, I'll do
something more broad to catch the SPL_SEPARATE_BSS=n case, and add the
ASSERTS that are missing.

-- 
Tom

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