Change mux parents to use struct mtk_parent instead of int. Since these clocks have mixed parents, we should be using struct mtk_parent which specifically handles this case.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7623.c | 777 +++++++++++++++++++------------------- 1 file changed, 390 insertions(+), 387 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index d62b9651fa6..dfe6f5e113e 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -375,399 +375,402 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_MMPLL_D2, - CLK_TOP_DMPLL_D2 -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int mm_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL1_D4 -}; - -static const int vdec_parents[] = { - CLK_XTAL, - CLK_TOP_VDECPLL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_VENCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int mfg_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_DMPLL_X2, - CLK_TOP_MSDCPLL, - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2 -}; - -static const int camtg_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8 -}; - -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_UNIVPLL3_D4 -}; - -static const int msdc30_parents[] = { - CLK_XTAL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, -}; - -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int dpi0_tve_parents[] = { - CLK_XTAL, - CLK_TOP_MIPIPLL, - CLK_TOP_MIPIPLL_D2, - CLK_TOP_MIPIPLL_D4, - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int dpi1_parents[] = { - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int hdmi_parents[] = { - CLK_XTAL, - CLK_TOP_HDMIPLL, - CLK_TOP_HDMIPLL_D2, - CLK_TOP_HDMIPLL_D3 -}; - -static const int apll_parents[] = { - CLK_XTAL, - CLK_TOP_AUDPLL, - CLK_TOP_AUDPLL_D4, - CLK_TOP_AUDPLL_D8, - CLK_TOP_AUDPLL_D16, - CLK_TOP_AUDPLL_D24, - CLK_XTAL, - CLK_XTAL -}; - -static const int rtc_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_32K_EXTERNAL, - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8 -}; - -static const int nfi2x_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_XTAL -}; - -static const int emmc_hclk_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D2 -}; - -static const int flash_parents[] = { - CLK_TOP_CLK26M_D8, - CLK_XTAL, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int di_parents[] = { - CLK_XTAL, - CLK_TOP_TVD2PLL, - CLK_TOP_TVD2PLL_D2, - CLK_XTAL -}; - -static const int nr_osd_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int hdmirx_bist_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_XTAL, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_VENCPLL, - CLK_XTAL -}; - -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D2, - CLK_TOP_UNIVPLL_D2 -}; - -static const int asm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 -}; - -static const int ms_card_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8, - CLK_TOP_SYSPLL4_D4 -}; - -static const int ethif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_DMPLL, - CLK_TOP_DMPLL_D2 -}; - -static const int hdmirx_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D52 -}; - -static const int cmsys_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL -}; - -static const int clk_8bdac_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_8BDAC, - CLK_XTAL, - CLK_XTAL -}; - -static const int aud2dvd_parents[] = { - CLK_TOP_AUD_48K_TIMING, - CLK_TOP_AUD_44K_TIMING -}; - -static const int padmclk_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL_D52, - CLK_TOP_UNIVPLL_D108, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIVPLL2_D32 -}; +#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL) +#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) -static const int aud_mux_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL_98M, - CLK_TOP_AUD2PLL_90M, - CLK_TOP_HADDS2PLL_98M, - CLK_TOP_AUD_EXTCK1_DIV, - CLK_TOP_AUD_EXTCK2_DIV +static const struct mtk_parent axi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D2), +}; + +static const struct mtk_parent mem_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent mm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), +}; + +static const struct mtk_parent vdec_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VDECPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent mfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_DMPLL_X2), + TOP_PARENT(CLK_TOP_MSDCPLL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), +}; + +static const struct mtk_parent camtg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent uart_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), +}; + +static const struct mtk_parent usb20_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), +}; + +static const struct mtk_parent msdc30_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent pmicspi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent scp_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent dpi0_tve_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MIPIPLL), + TOP_PARENT(CLK_TOP_MIPIPLL_D2), + TOP_PARENT(CLK_TOP_MIPIPLL_D4), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent dpi1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent hdmi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_HDMIPLL), + TOP_PARENT(CLK_TOP_HDMIPLL_D2), + TOP_PARENT(CLK_TOP_HDMIPLL_D3), +}; + +static const struct mtk_parent apll_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUDPLL), + TOP_PARENT(CLK_TOP_AUDPLL_D4), + TOP_PARENT(CLK_TOP_AUDPLL_D8), + TOP_PARENT(CLK_TOP_AUDPLL_D16), + TOP_PARENT(CLK_TOP_AUDPLL_D24), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent rtc_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_32K_EXTERNAL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), +}; + +static const struct mtk_parent nfi2x_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent emmc_hclk_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), +}; + +static const struct mtk_parent flash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D8), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent di_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_TVD2PLL), + TOP_PARENT(CLK_TOP_TVD2PLL_D2), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent nr_osd_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent hdmirx_bist_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_VENCPLL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent intdir_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), +}; + +static const struct mtk_parent asm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), +}; + +static const struct mtk_parent ms_card_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), +}; + +static const struct mtk_parent ethif_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_DMPLL), + TOP_PARENT(CLK_TOP_DMPLL_D2), +}; + +static const struct mtk_parent hdmirx_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), +}; + +static const struct mtk_parent cmsys_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent clk_8bdac_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_8BDAC), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent aud2dvd_parents[] = { + TOP_PARENT(CLK_TOP_AUD_48K_TIMING), + TOP_PARENT(CLK_TOP_AUD_44K_TIMING), +}; + +static const struct mtk_parent padmclk_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), + TOP_PARENT(CLK_TOP_UNIVPLL_D108), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), +}; + +static const struct mtk_parent aud_mux_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_AUD1PLL_98M), + TOP_PARENT(CLK_TOP_AUD2PLL_90M), + TOP_PARENT(CLK_TOP_HADDS2PLL_98M), + TOP_PARENT(CLK_TOP_AUD_EXTCK1_DIV), + TOP_PARENT(CLK_TOP_AUD_EXTCK2_DIV), }; -static const int aud_src_parents[] = { - CLK_TOP_AUD_MUX1_SEL, - CLK_TOP_AUD_MUX2_SEL +static const struct mtk_parent aud_src_parents[] = { + TOP_PARENT(CLK_TOP_AUD_MUX1_SEL), + TOP_PARENT(CLK_TOP_AUD_MUX2_SEL), }; static const struct mtk_composite top_muxes[] = { - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), - MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), - - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), - MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), - MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), - - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), - MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), - MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), - - MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), - MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), - MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), - - MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), - MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), - MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), - - MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), - MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), - MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), - - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), - MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), - MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), - MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), - - MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), - MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), - - MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), - MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_MUX_DOMAIN_SCPSYS), - - MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), - MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), - MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), - - MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), - MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), - MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), - MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), - - MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), - - MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), - MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), - MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), - - MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), - MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), - MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), - MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), - MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), - MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_MIXED_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, + CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), + MUX_GATE_MIXED_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, + CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), + + MUX_GATE_MIXED(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), + + MUX_GATE_MIXED(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), + + MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), + + MUX_GATE_MIXED(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), + MUX_GATE_MIXED_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, + CLK_MUX_DOMAIN_SCPSYS), + + MUX_GATE_MIXED(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), + + MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), + + MUX_MIXED(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), + + MUX_MIXED(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), + MUX_MIXED(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), + MUX_MIXED(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), + + MUX_GATE_MIXED(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), + MUX_GATE_MIXED(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), + MUX_GATE_MIXED(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), + MUX_GATE_MIXED(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), + MUX_GATE_MIXED(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), }; /* infracfg */ -- 2.43.0
