Change mux parents to use struct mtk_parent instead of int. Since these clocks have mixed parents, we should be using struct mtk_parent which specifically handles this case.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7629.c | 444 +++++++++++++++++++------------------- 1 file changed, 224 insertions(+), 220 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 85011f5327b..56f4c99d84b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -152,271 +152,275 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SGMIIPLL_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int sgmii_ref_1_parents[] = { - CLK_XTAL, - CLK_TOP_SGMIIPLL_D2 -}; - -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL_D7 -}; - -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL -}; - -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL -}; - -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M -}; - -static const int msdc30_1_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL) +#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) +#define VOID_PARENT PARENT(-1, 0) + +static const struct mtk_parent axi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent mem_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent eth_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent sgmii_ref_1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), +}; + +static const struct mtk_parent nfi_infra_parents[] = { + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), +}; + +static const struct mtk_parent flash_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent uart_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent spi1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + XTAL_PARENT(CLK_XTAL), +}; + +static const struct mtk_parent msdc30_0_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int ap2wbmcu_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent ap2wbmcu_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_DMPLL_D4 -}; +static const struct mtk_parent aud_intbus_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_DMPLL_D8 +static const struct mtk_parent pmicspi_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_DMPLL_D8), }; -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent scp_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int hif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent hif_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int sata_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent sata_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent usb20_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int aud1_parents[] = { - CLK_XTAL +static const struct mtk_parent aud1_parents[] = { + XTAL_PARENT(CLK_XTAL), }; -static const int irrx_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent irrx_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int crypto_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent crypto_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int gpt10m_parents[] = { - CLK_XTAL, - CLK_TOP_CLKXTAL_D4 +static const struct mtk_parent gpt10m_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), - MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), - MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE_MIXED(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), - MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), - MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), - MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), - MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_MUX_DOMAIN_SCPSYS), - MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), - MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_MIXED_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, + CLK_MUX_DOMAIN_SCPSYS), + MUX_GATE_MIXED(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), - MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), - MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), - MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), - MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), - MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), - MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), - MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; /* infracfg */ -- 2.43.0
