The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the 64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses. The physical addresses for these Address Windows across PCIe instances across SoCs is as follows:
+--------+----------------+----------------+----------------+----------------+ | SoC | PCIe0 | PCIe1 | PCIe2 | PCIe3 | +--------+----------------+----------------+----------------+----------------+ | AM64 | 0x6_0000_0000 | NA | NA | NA | | J722S | 0x6_0000_0000 | NA | NA | NA | | AM68 | NA | 0x41_0000_0000 | NA | NA | | J7200 | NA | 0x41_0000_0000 | NA | NA | | J721S2 | NA | 0x41_0000_0000 | NA | NA | | J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA | NA | | AM69 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J721E | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | +--------+----------------+----------------+----------------+----------------+ Two regions for a 1:1 mapping from virtual addresses to physical addresses catering to all of the above will be required, which are: 1. For AM64 and J722S SoCs => Start: 0x6_0000_0000 Size: 0x1_0000_0000 2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs => Start: 0x40_0000_0000 Size: 0x4_0000_0000 Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF includes the mapping for AM64 and J722S SoCs, only the second region mentioned above needs to be added. Hence, add the region to support 64-bit address space for PCIe. Signed-off-by: Siddharth Vadapalli <[email protected]> --- arch/arm/mach-k3/arm64/arm64-mmu.c | 16 ++++++++++++++++ arch/arm/mach-k3/include/mach/k3-ddr.h | 11 +++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c index f999af143fb..e032755db0d 100644 --- a/arch/arm/mach-k3/arm64/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64/arm64-mmu.c @@ -29,6 +29,22 @@ struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* + * PCIe 4 GB Address Window for AM64 and J722S SoCs starts + * from 0x6_0000_0000 and has a size of 0x1_0000_0000. + * Since this is already enabled by the 'Flash Peripherals' + * region above, we don't need to add it again. + * + * The PCIe 4 GB Address Windows for AM68, AM69, J7200, J721E, + * J721S2, J742S2 and J784S4 SoCs are enabled by the following + * region. + */ + .virt = 0x4000000000UL, + .phys = 0x4000000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */ .virt = CFG_SYS_SDRAM_BASE, .phys = CFG_SYS_SDRAM_BASE, diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h index 207e60b2763..6ac7f682fb8 100644 --- a/arch/arm/mach-k3/include/mach/k3-ddr.h +++ b/arch/arm/mach-k3/include/mach/k3-ddr.h @@ -8,11 +8,14 @@ #include <spl.h> -/* We need 3 extra entries for: - * SoC peripherals, flash and the sentinel value. +/* We need 4 extra entries for: + * 1. SoC peripherals + * 2. Flash + * 3. PCIe 4GB Windows for AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs + * 4. Sentinel value */ -#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3) -#define K3_MEM_MAP_FIRST_BANK_IDX 2 +#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 4) +#define K3_MEM_MAP_FIRST_BANK_IDX 3 int dram_init(void); int dram_init_banksize(void); -- 2.51.1
