This code has been changed to read the CPU speed information from the
CPR registers rather than the bootstrap registers. This is useful when
changing the clock speed to something other than the default on boot.
Signed-off-by: Mike Williams <m...@mikebwilliams.com>
---
arch/powerpc/cpu/ppc4xx/speed.c | 33 +++++++++++++------------------
arch/powerpc/include/asm/ppc460ex_gt.h | 15 +++++++++++++-
2 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 09d6671..2643fc0 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -328,38 +328,33 @@ void get_sys_info(sys_info_t *sysInfo)
*/
void get_sys_info (sys_info_t * sysInfo)
{
- unsigned long strp0;
- unsigned long strp1;
+ unsigned long pllc, plld, plbed, opbd, perd;
unsigned long temp;
unsigned long m;
unsigned long plbedv0;
/* Extract configured divisors */
- mfsdr(SDR0_SDSTP0, strp0);
- mfsdr(SDR0_SDSTP1, strp1);
-
- temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
- sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
- temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK);
- sysInfo->pllFwdDivB = get_cpr0_fwdv(temp);
- temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8;
- sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+ mfcpr(CPR0_PLLD, plld);
+ sysInfo->pllFwdDivA = get_cpr0_fwdv((plld & PLLD_FWDVA_MASK) >> 16);
+ sysInfo->pllFwdDivB = get_cpr0_fwdv((plld & PLLD_FWDVB_MASK) >> 8);
+ sysInfo->pllFbkDiv = get_cpr0_fbdv((plld & PLLD_FBDV_MASK) >> 24);
- temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26;
+ mfcpr(CPR0_OPBD0, opbd);
+ temp = ((opbd & OPBDV_MASK) >> 24);
sysInfo->pllOpbDiv = temp ? temp : 4;
- /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv
*/
- temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24;
+ mfcpr(CPR0_PERD, perd);
+ temp = ((perd & PERDV_MASK) >> 24);
sysInfo->pllExtBusDiv = temp ? temp : 4;
- temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29;
- plbedv0 = temp ? temp: 8;
+ mfcpr(CPR0_PLBED, plbed);
+ temp = ((plbed & PLBEDDV_MASK) >> 24);
+ plbedv0 = temp ? temp : 8;
/* Calculate 'M' based on feedback source */
- temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
- if (temp == 0) {
+ mfcpr(CPR0_PLLC, pllc);
+ if (((pllc & PLLC_FBSEL_MASK) >> 24) == 0) {
/* PLL internal feedback */
m = sysInfo->pllFbkDiv;
} else {
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h
b/arch/powerpc/include/asm/ppc460ex_gt.h
index 732fcac..25954b9 100644
--- a/arch/powerpc/include/asm/ppc460ex_gt.h
+++ b/arch/powerpc/include/asm/ppc460ex_gt.h
@@ -211,11 +211,24 @@
#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
-#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_PLBED 0x00000080 /* PLL PLB Ealry Clock Divider */
+
+#define CPR0_ICFG_RLI_MASK 0x80000000 /* CPR Reset Load Inhibit */
#define CPR0_PLLC_RST 0x80000000
#define CPR0_PLLC_ENG 0x40000000
+#define PLLC_FBSEL_MASK 0x03000000 /* PLLC Feedback Selection */
+
+#define PLLD_FBDV_MASK 0xff000000 /* PLL Feedback Divisor */
+#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
+
+#define PLBEDDV_MASK 0x07000000 /* PLB Early Divisor */
+#define OPBDV_MASK 0x03000000 /* OPB Clock Divisor Register */
+#define PERDV_MASK 0x03000000 /* Periferal Clock Divisor */
+#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
+
#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
--
1.7.3.4
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