This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
Signed-off-by: Ajay Bhargav <ajay.bhar...@einfochips.com>
---
Changes for v2:
- mvgpio.h removed
- function get_gpio_base moved to gpio.h
- error messages added
Changes for v3:
- Added mvgpio.h for common define based on CPU core subversion.
Changes for v4:
- not changed
Changes for v5:
- Added change history
Changes for v6:
- Renamed GPIO level defines (fixes compilation issues thanks to
Lei Wen)
drivers/gpio/Makefile | 1 +
drivers/gpio/mvgpio.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++
include/mvgpio.h | 77 +++++++++++++++++++++++++++++++++
3 files changed, 192 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 include/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 0000000..0cc8ed7
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhar...@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO 128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 0000000..8bc303b
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhar...@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVGPIO_H__
+#define __MVGPIO_H__
+
+#include <common.h>
+
+#define GPIO_LEVEL_SET 1
+#define GPIO_LEVEL_CLR 0
+
+#ifdef CONFIG_SHEEVA_88SV331xV5
+/*
+ * GPIO Register map for SHEEVA 88SV331xV5
+ */
+struct gpio_reg {
+ u32 gplr; /* Pin Level Register - 0x0000 */
+ u32 pad0[2];
+ u32 gpdr; /* Pin Direction Register - 0x000C */
+ u32 pad1[2];
+ u32 gpsr; /* Pin Output Set Register - 0x0018 */
+ u32 pad2[2];
+ u32 gpcr; /* Pin Output Clear Register - 0x0024 */
+ u32 pad3[2];
+ u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
+ u32 pad4[2];
+ u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
+ u32 pad5[2];
+ u32 gedr; /* Edge Detect Status Register - 0x0048 */
+ u32 pad6[2];
+ u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
+ u32 pad7[2];
+ u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
+ u32 pad8[2];
+ u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
+ Register - 0x006C */
+ u32 pad9[2];
+ u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
+ Register - 0x0078 */
+ u32 pad10[2];
+ u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
+ Register - 0x0084 */
+ u32 pad11[2];
+ u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
+ Register - 0x0090 */
+ u32 pad12[2];
+ u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
+};
+#else
+#error "CPU core subversion not defined"
+#endif
+
+#endif /* __MVGPIO_H__ */
--
1.7.0.4
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