On 10/06/2011 01:36 AM, Ilya Yanok wrote:
> DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
> enabled by default. So we have to take care and flush/invalidate the
> cache before/after the DMA operations.
>
> Signed-off-by: Ilya Yanok <ya...@emcraft.com>
Hi Ilya,
> ---
> drivers/net/davinci_emac.c | 47
> ++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 47 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
> index 222a0d0..b787213 100644
> --- a/drivers/net/davinci_emac.c
> +++ b/drivers/net/davinci_emac.c
> @@ -96,6 +96,40 @@ static volatile u_int8_t active_phy_addr = 0xff;
>
> phy_t phy;
>
> +#ifdef DAVINCI_EMAC_DCACHE
> +static inline void davinci_flush(void *addr, int size)
> +{
> + flush_dcache_range((unsigned long)addr,
> + (unsigned long)addr + size);
> +}
There is no check with the cache linesize. I get this error:
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x5c0200a0
Should we not be sure that size is rounded up to align with the cache
line size ?
Best regards,
Stefano Babic
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