On Wed Jan 11, 2012 at 11:47:27AM +0100, Marek Vasut wrote: > > On Tue Jan 10, 2012 at 09:07:58PM +0100, Marek Vasut wrote: > > > > The current implementation invalidates the cache instead of flushing > > > > it. This causes problems on platforms where the spl/u-boot is already > > > > loaded to the RAM, with caches enabled by a first stage bootloader. > > > > > > What platforms are affected? > > > > It is causing a problem on the hawkboard, where the spl is loaded > > directly to the RAM by a rom bootloader. We did not see this earlier > > since cpu_init_crit was not getting called due to > > CONFIG_SKIP_LOWLEVEL_INIT. > > > > -sughosh > > I see ... why don't you directly load U-Boot to DRAM then ?
The rom bootloader(rbl) uses a different ecc layout from the one used by the davinci nand driver(u-boot and linux). Using rbl to load the u-boot to dram would mean that i have to use the TI's external flashing utility every time i upgrade u-boot. Also, i would not be able to flash u-boot from the kernel. -sughosh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot