>-----Original Message----- >From: Simon Glass [mailto:s...@chromium.org] >Sent: Tuesday, April 03, 2012 7:19 AM >To: U-Boot Mailing List >Cc: Tom Warren; Stephen Warren; Wei Ni; Simon Glass; Stephen Warren >Subject: [PATCH v3 18/23] tegra: Turn off power detect in board init > >From: Wei Ni <w...@nvidia.com> > >Tegra core power rail has leakage voltage around 0.2V while system in >suspend mode. The source of the leakage should be coming from PMC power >detect logic for IO rails power detection. >That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' >to PWR_DET (APBDEV_PMC_PWR_DET_0).
Signe-off-by: Wei Ni <w...@nvidia.com> > >Signed-off-by: Simon Glass <s...@chromium.org> >--- >Changes in v3: >- Fix CONFIG_TEGRA_I2C define ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ----------------------------------------------------------------------------------- _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
