Hi Marek, [...]
>> - Why was the change made in the first place and for what OOT port? > > Change of a DRAM configuration register that enabled additional > address bit, at address 512MB of DRAM. Though this caused memory hole > on our M28 module with 256MB of DRAM, which _is_ mainline. X board is > OOT and never will be mainlined I guess. I still do not understand this fully. What exactly is this "memory hole" and why is it fatal? As far as I can remember, there are always some holes in the adress map, so why is this special? Apart from that, I think most of these answers should go into the commit message to understand what is happening. Thanks in advance Detlev -- Every generation laughs at the old fashions, but follows religiously the new. -- Henry David Thoreau -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot