Dear Detlev Zundel, > Hi Marek, > > [...] > > >> - Why was the change made in the first place and for what OOT port? > > > > Change of a DRAM configuration register that enabled additional > > address bit, at address 512MB of DRAM. Though this caused memory hole > > on our M28 module with 256MB of DRAM, which _is_ mainline. X board is > > OOT and never will be mainlined I guess. > > I still do not understand this fully. What exactly is this "memory > hole" and why is it fatal? As far as I can remember, there are always > some holes in the adress map, so why is this special?
No, this one created this layout on our 256 MB module: [chunk of memory][<- same thing][chunk of memory][<- same thing] so get_ram_size() didn't work with it and it actually overwrote part of the U- Boot etc. > > Apart from that, I think most of these answers should go into the commit > message to understand what is happening. Agreed > Thanks in advance > Detlev Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot