On 8/14/26 8:28 PM, Ralph Siemsen wrote:
[...]
@@ -250,7 +250,11 @@ static int cadence_spi_probe(struct udevice *bus)
return ret;
#endif
} else {
- priv->ref_clk_hz = clk_get_rate(&clk);
+ ret = clk_enable_bulk(&clks);
Some sort of clk_disable_bulk() seems to be missing.
Fail path which disables the clock seems to be missing too in this function.
+ if (ret)
+ dev_warn(bus, "failed clk_enable_bulk\n");
+
+ priv->ref_clk_hz = clk_get_rate(&clks.clks[0]);
Can the refclock be second or later (not first) clock in the list of
multiple clock in DT ? If yes, then the clk_get_rate[0] will return
bogus rate for another clock.
