Add support for the nord NW Global Clock Controller (NWGCC). Implement the qcom,nord-nwgcc driver to provide clocks, resets and power domains required by nord peripherals.
Signed-off-by: Aswin Murugan <[email protected]> --- drivers/clk/qcom/Kconfig | 9 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-nord-nwgcc.c | 100 ++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 drivers/clk/qcom/clock-nord-nwgcc.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index c10bb8186e9..6266f4a15b3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -81,6 +81,15 @@ config CLK_QCOM_NORD_SEGCC EMAC and QUPv3 clocks and resets exposed by the SEGCC hardware block. +config CLK_QCOM_NORD_NWGCC + bool "Qualcomm Nord NWGCC" + select CLK_QCOM + help + Say Y here to enable support for the North-West Global Clock + Controller on the Snapdragon Nord SoC. This driver supports the + camera, display, EVA, video, and GPU clocks and resets exposed by + the NWGCC hardware block. + config CLK_QCOM_QCM2290 bool "Qualcomm QCM2290 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e7c6e5fe35b..c9795377d1f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o obj-$(CONFIG_CLK_QCOM_NORD) += clock-nord-gcc.o obj-$(CONFIG_CLK_QCOM_NORD_NEGCC) += clock-nord-negcc.o obj-$(CONFIG_CLK_QCOM_NORD_SEGCC) += clock-nord-segcc.o +obj-$(CONFIG_CLK_QCOM_NORD_NWGCC) += clock-nord-nwgcc.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o diff --git a/drivers/clk/qcom/clock-nord-nwgcc.c b/drivers/clk/qcom/clock-nord-nwgcc.c new file mode 100644 index 00000000000..e7d189d07e6 --- /dev/null +++ b/drivers/clk/qcom/clock-nord-nwgcc.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,nord-nwgcc.h> +#include "clock-qcom.h" + +static const struct gate_clk nord_nwgcc_clks[] = { + GATE_CLK_POLLED(NW_GCC_CAMERA_TRIG_CLK, 0x16034, BIT(0), 0x16034), + GATE_CLK_POLLED(NW_GCC_DISP_0_TRIG_CLK, 0x1801c, BIT(0), 0x1801c), + GATE_CLK_POLLED(NW_GCC_DISP_1_TRIG_CLK, 0x1901c, BIT(0), 0x1901c), + GATE_CLK_POLLED(NW_GCC_EVA_TRIG_CLK, 0x1b028, BIT(0), 0x1b028), + GATE_CLK_POLLED(NW_GCC_GPU_2_GPLL0_CLK_SRC, 0x76000, BIT(6), 0x24150), + GATE_CLK_POLLED(NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC,0x76000, BIT(7), 0x24158), + GATE_CLK_POLLED(NW_GCC_GPU_2_HSCNOC_GFX_CLK, 0x2400c, BIT(0), 0x2400c), + GATE_CLK_POLLED(NW_GCC_GPU_GPLL0_CLK_SRC, 0x76000, BIT(4), 0x23150), + GATE_CLK_POLLED(NW_GCC_GPU_GPLL0_DIV_CLK_SRC, 0x76000, BIT(5), 0x23158), + GATE_CLK_POLLED(NW_GCC_GPU_SMMU_VOTE_CLK, 0x86038, BIT(0), 0x86038), + GATE_CLK_POLLED(NW_GCC_MMU_1_TCU_VOTE_CLK, 0x86040, BIT(0), 0x86040), + + GATE_CLK(NW_GCC_ACMU_MUX_CLK, 0x1f01c, BIT(0)), + GATE_CLK(NW_GCC_CAMERA_HF_AXI_CLK, 0x16008, BIT(0)), + GATE_CLK(NW_GCC_CAMERA_SF_AXI_CLK, 0x1601c, BIT(0)), + GATE_CLK(NW_GCC_DISP_0_HF_AXI_CLK, 0x18008, BIT(0)), + GATE_CLK(NW_GCC_DISP_1_HF_AXI_CLK, 0x19008, BIT(0)), + GATE_CLK(NW_GCC_DPRX0_AXI_HF_CLK, 0x29004, BIT(0)), + GATE_CLK(NW_GCC_DPRX1_AXI_HF_CLK, 0x2a004, BIT(0)), + GATE_CLK(NW_GCC_EVA_AXI0C_CLK, 0x1b01c, BIT(0)), + GATE_CLK(NW_GCC_EVA_AXI0_CLK, 0x1b008, BIT(0)), + GATE_CLK(NW_GCC_FRQ_MEASURE_REF_CLK, 0x1f008, BIT(0)), + GATE_CLK(NW_GCC_GP1_CLK, 0x20000, BIT(0)), + GATE_CLK(NW_GCC_GP2_CLK, 0x21000, BIT(0)), + GATE_CLK(NW_GCC_GPU_HSCNOC_GFX_CLK, 0x2300c, BIT(0)), + GATE_CLK(NW_GCC_HSCNOC_GPU_2_AXI_CLK, 0x24160, BIT(0)), + GATE_CLK(NW_GCC_HSCNOC_GPU_AXI_CLK, 0x23160, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI0C_CLK, 0x1a01c, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI0_CLK, 0x1a008, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI1_CLK, 0x1a030, BIT(0)), +}; + +static int nord_nwgcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_nwgcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map nord_nwgcc_resets[] = { + [NW_GCC_CAMERA_BCR] = { 0x16000 }, + [NW_GCC_DISPLAY_0_BCR] = { 0x18000 }, + [NW_GCC_DISPLAY_1_BCR] = { 0x19000 }, + [NW_GCC_DPRX0_BCR] = { 0x29000 }, + [NW_GCC_DPRX1_BCR] = { 0x2a000 }, + [NW_GCC_EVA_BCR] = { 0x1b000 }, + [NW_GCC_GPU_2_BCR] = { 0x24000 }, + [NW_GCC_GPU_BCR] = { 0x23000 }, + [NW_GCC_VIDEO_BCR] = { 0x1a000 }, +}; + +static struct msm_clk_data nord_nwgcc_data = { + .resets = nord_nwgcc_resets, + .num_resets = ARRAY_SIZE(nord_nwgcc_resets), + .clks = nord_nwgcc_clks, + .num_clks = ARRAY_SIZE(nord_nwgcc_clks), + + .enable = nord_nwgcc_enable, +}; + +static const struct udevice_id gcc_nord_nwgcc_of_match[] = { + { + .compatible = "qcom,nord-nwgcc", + .data = (ulong)&nord_nwgcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord_nwgcc) = { + .name = "gcc_nord_nwgcc", + .id = UCLASS_NOP, + .of_match = gcc_nord_nwgcc_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; -- 2.34.1
