CPM5 Host0 and Host1 each expose PCIe config space (ECAM) inside their 4 GiB NoC address slot, at 0x600000000 and 0x700000000 respectively. Per the DT "cfg" reg and the PCIe ECAM spec (256 bus numbers x 1 MiB per bus), each window is 256 MiB. Config space accesses must not be cached, reordered, or speculatively issued, so map each ECAM window as Device memory (MT_DEVICE_NGNRNE).
Rather than mapping 0x600000000-0xe00000000 only when CONFIG_PCIE_AMD_CPM is enabled, add it as a baseline Normal/cacheable entry unconditionally: this NoC/PL address space is shared by more than CPM (PL fabric AXI space, other NoC-attached peripherals, etc.), so it needs coverage regardless of which PCIe controllers are built in. The two CPM5 ECAM sub-ranges are then overlaid as Device memory on top of that baseline only when PCIE_AMD_CPM is enabled. Update VERSAL_MEM_MAP_USED to match: 3 entries when PCIE_AMD_CPM is disabled, 5 when it's enabled (+2 ECAM overlays). Co-developed-by: Uday Hegde <[email protected]> Signed-off-by: Uday Hegde <[email protected]> Signed-off-by: Pranav Sanwal <[email protected]> --- arch/arm/mach-versal/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 7521d45bc1a..5dbd0fcc438 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -20,7 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(PCIE_AMD_CPM) +#define VERSAL_MEM_MAP_USED 5 +#else #define VERSAL_MEM_MAP_USED 3 +#endif #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -55,6 +59,22 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN +#if CONFIG_IS_ENABLED(PCIE_AMD_CPM) + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x010000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x700000000UL, + .phys = 0x700000000UL, + .size = 0x010000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN +#endif } }; -- 2.43.7
