From: Tze Yee Ng <[email protected]>
Add UHS-I PHY and controller timing so SD cards and eMMC can run in the
higher speed modes on the Agilex5 SoCDK and its 013B and modular
variants:
- SoCDK: DDR50 (emmc-ddr) timing so SD cards / eMMC can run in UHS-I
DDR50 / DDR52 mode; advertise sd-uhs-ddr50 on the SD board and
mmc-ddr-1_8v on the eMMC board.
- 013B: drop no-1-8-v to allow 1.8V signalling and add SDR104
(emmc-hs200) and DDR50 (emmc-ddr) timing; advertise sd-uhs-sdr50,
sd-uhs-sdr104 and sd-uhs-ddr50.
- Modular: advertise sd-uhs-sdr50, sd-uhs-sdr104 and sd-uhs-ddr50 and
add DDR50 (emmc-ddr) timing (phony_dqs_timing = 0 re-centres the
returning data on the longer SoM SD path).
Signed-off-by: Tze Yee Ng <[email protected]>
---
.../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 13 ++++++++++
.../socfpga_agilex5_socdk_013b-u-boot.dtsi | 24 +++++++++++++++++--
arch/arm/dts/socfpga_agilex5_socdk_013b.dts | 4 +++-
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 13 ++++++++++
.../arm/dts/socfpga_agilex5_socdk_modular.dts | 20 ++++++++++++++++
5 files changed, 71 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index c03f78b2fdf..1cd54e29679 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -114,6 +114,7 @@
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
+ sd-uhs-ddr50;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&sd_io_1v8_reg>;
max-frequency = <200000000>;
@@ -153,6 +154,18 @@
cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+ /* SD card UHS-I DDR50 mode & eMMC DDR52 mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-ddr = <0x00580000>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-ddr = <0x81a40040>;
+ cdns,phy-dll-master-ctrl-emmc-ddr = <0xa00004>;
+ cdns,phy-dll-slave-ctrl-emmc-ddr = <0x60>;
+ cdns,phy-ctrl-emmc-ddr = <0x4010>;
+ cdns,phy-dq-timing-delay-emmc-ddr = <0x10000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-ddr = <0xf1c1800f>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-ddr = <0x00020000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-ddr = <0x11000000>;
+ cdns,ctrl-hrs07-timing-delay-emmc-ddr = <0x00090001>;
+
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
index 75d51ef06e3..819e0ba9798 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
@@ -121,14 +121,12 @@
status = "okay";
no-mmc;
- no-1-8-v;
disable-wp;
cap-sd-highspeed;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&sd_io_1v8_reg>;
max-frequency = <200000000>;
sdhci-caps = <0x00000000 0x0000c800>;
- sdhci-caps-mask = <0x00002007 0x0000ff00>;
/* SD card default speed (DS) and UHS-I SDR12 mode timing configuration
*/
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
@@ -153,6 +151,28 @@
cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>;
+ /* SD card UHS-I SDR104 mode timing configuration */
+ cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>;
+ cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
+ cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
+ cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
+ cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+
+ /* SD card UHS-I DDR50 mode & eMMC DDR52 mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-ddr = <0x00580000>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-ddr = <0x81a40040>;
+ cdns,phy-dll-master-ctrl-emmc-ddr = <0xa00004>;
+ cdns,phy-dll-slave-ctrl-emmc-ddr = <0x60>;
+ cdns,phy-ctrl-emmc-ddr = <0x4010>;
+ cdns,phy-dq-timing-delay-emmc-ddr = <0x10000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-ddr = <0xf1c1800f>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-ddr = <0x00020000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-ddr = <0x11000000>;
+ cdns,ctrl-hrs07-timing-delay-emmc-ddr = <0x00090001>;
+
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
b/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
index 9605fa4cb00..1bec13d998e 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
@@ -90,11 +90,13 @@
&mmc {
status = "okay";
bus-width = <4>;
- no-1-8-v;
cap-sd-highspeed;
cap-mmc-highspeed;
disable-wp;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ sdhci-caps-mask = <0x00002000 0x0000ff00>;
cdns,phy-use-ext-lpbk-dqs = <1>;
cdns,phy-use-lpbk-dqs = <1>;
cdns,phy-use-phony-dqs = <1>;
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
index c06781064ca..6c608cfc562 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
@@ -25,6 +25,7 @@
disable-wp;
non-removable;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
@@ -71,4 +72,16 @@
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>;
cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>;
cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>;
+
+ /* SD card UHS-I DDR50 mode & eMMC DDR52 mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-ddr = <0x00580000>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-ddr = <0x81a40040>;
+ cdns,phy-dll-master-ctrl-emmc-ddr = <0xa00004>;
+ cdns,phy-dll-slave-ctrl-emmc-ddr = <0x60>;
+ cdns,phy-ctrl-emmc-ddr = <0x4010>;
+ cdns,phy-dq-timing-delay-emmc-ddr = <0x10000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-ddr = <0xf1c1800f>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-ddr = <0x00020000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-ddr = <0x11000000>;
+ cdns,ctrl-hrs07-timing-delay-emmc-ddr = <0x00090001>;
};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_modular.dts
b/arch/arm/dts/socfpga_agilex5_socdk_modular.dts
index 032e40fc639..30a5a749d1d 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_modular.dts
@@ -33,6 +33,9 @@
no-mmc;
disable-wp;
cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&sd_io_1v8_reg>;
max-frequency = <200000000>;
@@ -71,5 +74,22 @@
cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+ /* SD card UHS-I DDR50 mode & eMMC DDR52 mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-ddr = <0x00580000>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-ddr = <0x81a40040>;
+ cdns,phy-dll-master-ctrl-emmc-ddr = <0xa00004>;
+ cdns,phy-dll-slave-ctrl-emmc-ddr = <0x60>;
+ /*
+ * Modular SoM: PHONY_DQS_TIMING (PHY_CTRL[9:4]) = 0 instead of the
+ * default 1. The longer SD path offsets the returning DDR data from the
+ * phony strobe; re-centring it stops one DDR beat collapsing onto both.
+ */
+ cdns,phy-ctrl-emmc-ddr = <0x4000>;
+ cdns,phy-dq-timing-delay-emmc-ddr = <0x10000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-ddr = <0xf1c1800f>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-ddr = <0x00020000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-ddr = <0x11000000>;
+ cdns,ctrl-hrs07-timing-delay-emmc-ddr = <0x00090001>;
+
bootph-all;
};
--
2.43.7
