From: Alice Guo <[email protected]> Add 1G SGMII mode configuration for i.MX95 platform in ENETC driver.
Note that 10/100 mode is not supported. Signed-off-by: Alice Guo <[email protected]> --- drivers/net/fsl_enetc.c | 19 +++++++++++++++++++ drivers/net/fsl_enetc.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 6f7829858ec..13f975c417a 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -36,6 +36,11 @@ static inline int xpcs_phy_usxgmii_pma_config(struct udevice *dev) { return 0; } + +static inline int xpcs_phy_sgmii_1g_config(struct udevice *dev) +{ + return 0; +} #endif #define ENETC_DRIVER_NAME "enetc_eth" @@ -388,6 +393,9 @@ static int enetc_init_sgmii(struct udevice *dev) if (!enetc_has_imdio(dev)) return 0; + if (priv->uclass_id == PHY_INTERFACE_MODE_SGMII && enetc_is_imx95(dev)) + return xpcs_phy_sgmii_1g_config(dev); + if (priv->uclass_id == PHY_INTERFACE_MODE_2500BASEX) is2500 = true; @@ -483,6 +491,14 @@ static void enetc_setup_mac_iface(struct udevice *dev, if_mode &= ~ENETC_PM_IF_IFMODE_MASK_LS; enetc_write_mac_port(dev, ENETC_PM_IF_MODE, if_mode); break; + case PHY_INTERFACE_MODE_SGMII: + if_mode = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); + if (enetc_is_imx95(dev)) { + if_mode &= ~(ENETC_PM_IF_IFMODE_MASK_IMX | ENETC_PM_IF_MODE_AN_ENA); + if_mode |= IFMODE_SGMII; + } + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, if_mode); + break; }; } @@ -566,6 +582,9 @@ static int enetc_config_phy(struct udevice *dev) if (enetc_is_imx95(dev)) supported |= PHY_10G_FEATURES; + if (priv->uclass_id == PHY_INTERFACE_MODE_SGMII && enetc_is_imx95(dev)) + supported &= ~(PHY_100BT_FEATURES | PHY_10BT_FEATURES); + priv->phy->supported &= supported; priv->phy->advertising &= supported; diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 6d868e82f8c..bcab6f252a0 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -104,6 +104,7 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PM_IFM_FULL_DPX_IMX BIT(6) #define ENETC_PM_IFM_FULL_DPX_LS BIT(12) #define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0) +#define IFMODE_SGMII 5 #define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0) /* i.MX95 specific registers */ -- 2.34.1
