The CNTP base address points one byte before generic counter region 1 memory address, which is unusual. Since U-Boot on R-Car Gen5 A-core never runs in EL3, the code which would access this memory address is never executed. Drop both the CNTP base address macro, and the unused code.
Signed-off-by: Marek Vasut <[email protected]> --- Cc: Nobuhiro Iwamatsu <[email protected]> Cc: Tom Rini <[email protected]> Cc: [email protected] --- .../include/mach/rcar-gen5-base.h | 5 ----- board/renesas/common/gen5-common.c | 20 ------------------- 2 files changed, 25 deletions(-) diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h index 35b0d00e45c..748fc028999 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h @@ -17,11 +17,6 @@ #define TMU_BASE 0x1C030000 #endif -/* Arm Generic Timer */ -#define CNTCR_BASE 0x1C000FFF /* Region 0 */ -#define CNTFID0 (CNTCR_BASE + 0x020) -#define CNTCR_EN BIT(0) - /* Reset */ #define RST_BASE 0xC1320000 /* Domain0 */ #define RST_SWSRES1A (RST_BASE + 0x410) diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c index 5160b32e2e3..51bab2aa19e 100644 --- a/board/renesas/common/gen5-common.c +++ b/board/renesas/common/gen5-common.c @@ -12,18 +12,6 @@ #include <asm-generic/u-boot.h> #include <linux/errno.h> -static void init_generic_timer(void) -{ - const u32 freq = CONFIG_SYS_CLK_FREQ; - - /* Update memory mapped and register based freqency */ - asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); - writel(freq, CNTFID0); - - /* Enable counter */ - setbits_le32(CNTCR_BASE, CNTCR_EN); -} - static void init_gic_v3(void) { /* GIC v3 power on */ @@ -37,14 +25,6 @@ static void init_gic_v3(void) writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); } -int mach_cpu_init(void) -{ - if (current_el() == 3) - init_generic_timer(); - - return 0; -} - int board_early_init_f(void) { return 0; -- 2.53.0
