From: Dinesh Maniyam <[email protected]>
Add device tree, U-Boot dtsi and a defconfig for the Agilex5 E-Series
013B SoCDK (DK-A5E013BM16AEA). The board uses a 64 MB QSPI flash with
a different layout than the base SoCDK, so it needs its own DT and
defconfig rather than a DT overlay on the existing target.
Keep Linux-facing MMC essentials in the .dts and Cadence PHY timing in
the U-Boot dtsi, matching the base Agilex5 SoCDK split. Advertise
sd-uhs-sdr50 with 1.8 V signalling (sd_io_1v8_reg); leave SDR104 and
DDR50 to a separate UHS PHY timing series. Alias ethernet0 to the
enabled gmac2 port and use snps,dwxgmac-mdio for its MDIO child.
Guard the &binman { /delete-node/ kernel; } cleanup with CONFIG_FIT so
non-FIT SoCFPGA defconfigs that compile every socfpga_*.dtb continue
to build.
Signed-off-by: Dinesh Maniyam <[email protected]>
---
Changes in v2:
- Squash review follow-ups into the board-add commit
- Drop no-1-8-v; advertise sd-uhs-sdr50 only in -u-boot.dtsi
(DK-A5E013BM16AEA supports 1.8 V switching). Leave SDR104 and
DDR50 for a later series
- Follow base SoCDK MMC split (Linux essentials in .dts, Cadence
timing in -u-boot.dtsi); /delete-property/ cap-mmc-highspeed
- Change gmac2 MDIO compatible to snps,dwxgmac-mdio
- Alias ethernet0 to enabled gmac2 only
Link:
https://lore.kernel.org/all/[email protected]/
arch/arm/dts/Makefile | 3 +-
.../socfpga_agilex5_socdk_013b-u-boot.dtsi | 217 ++++++++++++++++++
arch/arm/dts/socfpga_agilex5_socdk_013b.dts | 153 ++++++++++++
board/intel/agilex5-socdk/MAINTAINERS | 3 +
configs/socfpga_agilex5_013b_defconfig | 7 +
5 files changed, 382 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_013b.dts
create mode 100644 configs/socfpga_agilex5_013b_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2b65cd9105c..483ab671895 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -427,7 +427,8 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex5_socdk.dtb \
- socfpga_agilex5_socdk_emmc.dtb \
+ socfpga_agilex5_socdk_013b.dtb \
+ socfpga_agilex5_socdk_emmc.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
new file mode 100644
index 00000000000..f77a231e5af
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions for Agilex5 SocDK 013B
+ *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include "socfpga_agilex5-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@0x20000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x20000450 0x00000010>;
+ status = "disabled";
+ };
+ };
+
+ /*
+ * Both Memory base address and size default info is retrieved from HW
setting.
+ * Reconfiguration / Overwrite these info can be done with examples
below.
+ *
+ * When LPDDR ECC is enabled, the last 1/8 of the memory region must
+ * be reserved for the Inline ECC buffer.
+ *
+ * Example for memory size with 2GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>;
+ * };
+ *
+ * Example for memory size with 8GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x80000000>;
+ * };
+ *
+ * Example for memory size with 32GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>;
+ * };
+ *
+ * Example for memory size with 512GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>,
+ * <0x88 0x00000000 0x78 0x00000000>;
+ * };
+ *
+ * Example for memory size with 2GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x70000000>;
+ * };
+ *
+ * Example for memory size with 8GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x40000000>;
+ * };
+ */
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,"/memory";
+ };
+};
+
+&flash0 {
+ bootph-all;
+ /delete-property/ cdns,read-delay;
+};
+
+&i2c0 {
+ status = "okay";
+ bootph-all;
+};
+
+&i2c1 {
+ status = "okay";
+ bootph-all;
+};
+
+&i2c3 {
+ status = "okay";
+ bootph-all;
+};
+
+&i3c0 {
+ bootph-all;
+};
+
+&i3c1 {
+ bootph-all;
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&gpio1 {
+ portb: gpio-controller@0 {
+ bootph-all;
+ };
+};
+
+&sd_emmc_power {
+ bootph-all;
+};
+
+&sd_io_1v8_reg {
+ gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+};
+
+&mmc {
+ status = "okay";
+
+ no-mmc;
+ /delete-property/ cap-mmc-highspeed;
+ disable-wp;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ vmmc-supply = <&sd_emmc_power>;
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ max-frequency = <200000000>;
+ sdhci-caps = <0x00000000 0x0000c800>;
+ sdhci-caps-mask = <0x00002006 0x0000ff00>;
+
+ /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration
*/
+ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
+ cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
+ cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
+ cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
+
+ /* SD card high speed and UHS-I SDR25 mode timing configuration */
+ cdns,phy-dqs-timing-delay-sd-hs = <0x780001>;
+ cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>;
+ cdns,phy-dq-timing-delay-sd-hs = <0x10000001>;
+ cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>;
+ cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>;
+
+ /* SD card UHS-I SDR50 mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>;
+ cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>;
+ cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
+ cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>;
+
+ bootph-all;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+ bootph-all;
+};
+
+&timer1 {
+ status = "okay";
+ bootph-all;
+};
+
+&timer2 {
+ status = "okay";
+ bootph-all;
+};
+
+&timer3 {
+ status = "okay";
+ bootph-all;
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+ bootph-all;
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&watchdog2 {
+ status = "okay";
+};
+
+&watchdog3 {
+ status = "okay";
+};
+
+&watchdog4 {
+ status = "okay";
+};
+
+#if defined(CONFIG_FIT) && !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&binman {
+ /delete-node/ kernel;
+};
+#endif
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
b/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
new file mode 100644
index 00000000000..a96c616ab3f
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk_013b.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 013B SoCDK";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "hps_led0";
+ gpios = <&porta 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&porta 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac2_phy0>;
+ max-frame-size = <9000>;
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ rxc-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txc-skew-ps = <0>;
+ txen-skew-ps = <60>;
+ txd0-skew-ps = <60>;
+ txd1-skew-ps = <60>;
+ txd2-skew-ps = <60>;
+ txd3-skew-ps = <60>;
+ };
+ };
+};
+
+&i3c0 {
+ status = "okay";
+};
+
+&i3c1 {
+ status = "okay";
+};
+
+&mmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&qspi {
+ status = "okay";
+ cdns,fifo-depth = <0x400>;
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width=<4>;
+ spi-rx-bus-width=<4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ rsu-handle = <&qspi_boot>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x00c00000>;
+ };
+
+ root: partition@c00000 {
+ label = "root";
+ reg = <0x00c00000 0x03400000>;
+ };
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&usb31 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/board/intel/agilex5-socdk/MAINTAINERS
b/board/intel/agilex5-socdk/MAINTAINERS
index 30d8815d202..d78e2fa1b67 100644
--- a/board/intel/agilex5-socdk/MAINTAINERS
+++ b/board/intel/agilex5-socdk/MAINTAINERS
@@ -7,4 +7,7 @@ S: Maintained
F: board/intel/agilex5-socdk/
F: include/configs/socfpga_agilex5_socdk.h
F: configs/socfpga_agilex5_defconfig
+F: configs/socfpga_agilex5_013b_defconfig
F: configs/socfpga_agilex5_nand2_defconfig
+F: arch/arm/dts/socfpga_agilex5_socdk_013b.dts
+F: arch/arm/dts/socfpga_agilex5_socdk_013b-u-boot.dtsi
diff --git a/configs/socfpga_agilex5_013b_defconfig
b/configs/socfpga_agilex5_013b_defconfig
new file mode 100644
index 00000000000..4aeaf6374e3
--- /dev/null
+++ b/configs/socfpga_agilex5_013b_defconfig
@@ -0,0 +1,7 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_013b"
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0a00000
+# CONFIG_PHY_MARVELL is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
--
2.43.7
