The topckgen and gate clock U_BOOT_DRIVER entries only differ by their of_match table: they share the same probe, ops, private data and flags. Merge them into a single mt8189-clk driver, the way clk-mt8366.c already does, so that a new clock block only needs a new of_match entry.
The gate entries, which used to be written on a single line, are split over two lines, for consistency with the topckgen entry and to keep the lines short. No functional change. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt8189.c | 57 ++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index 05e5593c714..6a69c78f857 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1986,11 +1986,39 @@ static const struct udevice_id mt8189_apmixed[] = { { } }; -static const struct udevice_id mt8189_topckgen_compat[] = { +static const struct udevice_id mt8189_clk_compat[] = { { .compatible = "mediatek,mt8189-topckgen", .data = (ulong)&mt8189_topckgen_clk_tree, }, + { + .compatible = "mediatek,mt8189-peri-ao", + .data = (ulong)&perao_clks_tree, + }, + { + .compatible = "mediatek,mt8189-iic-wrap", + .data = (ulong)&imp_clks_tree, + }, + { + .compatible = "mediatek,mt8189-dispsys", + .data = (ulong)&mm_clks_tree, + }, + { + .compatible = "mediatek,mt8189-mm-infra", + .data = (ulong)&mminfra_config_clks_tree, + }, + { + .compatible = "mediatek,mt8189-ufscfg-ao", + .data = (ulong)&ufs_config_ao_clks_tree, + }, + { + .compatible = "mediatek,mt8189-ufscfg-pdn", + .data = (ulong)&ufs_config_pdn_clks_tree, + }, + { + .compatible = "mediatek,mt8189-vlpcfg-ao", + .data = (ulong)&vlpcfg_ao_clks_tree, + }, { } }; @@ -2002,17 +2030,6 @@ static const struct udevice_id mt8189_vlpckgen[] = { { } }; -static const struct udevice_id of_match_mt8189_clk_gate[] = { - { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_tree }, - { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_tree }, - { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_tree }, - { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_tree }, - { .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_tree }, - { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_tree }, - { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_tree }, - { } -}; - U_BOOT_DRIVER(mt8189_clk_apmixedsys) = { .name = "mt8189-apmixedsys", .id = UCLASS_CLK, @@ -2023,10 +2040,10 @@ U_BOOT_DRIVER(mt8189_clk_apmixedsys) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mt8189_clk_topckgen) = { - .name = "mt8189-topckgen", +U_BOOT_DRIVER(mt8189_clk) = { + .name = "mt8189-clk", .id = UCLASS_CLK, - .of_match = mt8189_topckgen_compat, + .of_match = mt8189_clk_compat, .probe = mtk_clk_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, @@ -2042,13 +2059,3 @@ U_BOOT_DRIVER(mt8189_clk_vlpckgen) = { .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; - -U_BOOT_DRIVER(mt8189_clk_gate) = { - .name = "mt8189-gate-clk", - .id = UCLASS_CLK, - .of_match = of_match_mt8189_clk_gate, - .probe = mtk_clk_probe, - .priv_auto = sizeof(struct mtk_clk_priv), - .ops = &mtk_clk_topckgen_ops, - .flags = DM_FLAG_PRE_RELOC, -}; -- 2.55.0
