Hi Vladimir, On Thu, Oct 01, 2026 at 05:55:29PM +0300, Vladimir Oltean wrote: > So it's *not* that for 25G you need to multiply by 2 and for 10G you > don't. It's the fact that a single PLL can produce a single clock net > frequency, and no clock net frequency can satisfy both 10G and 25G.
Thanks for the explanation. I'll update it into the v6 comments, something like: * A PLL makes one clock net, and each lane takes its rate from the * clock net of one PLL, through its own BY_N_RATE_SEL. 25GE and 100GE * lanes run at 25.78125 Gbaud, twice the 12.890625 GHz clock net of * PLLF. 40GE lanes run at 10.3125 Gbaud, which no ratio of 12.890625 * GHz gives: they need the 10.3125 GHz clock net, which only PLLS * makes (PLLnCR1[FRATE_SEL]=00110b). So the lanes move to PLLS. > Technically "does not power PLLS up" rather than "powers it down". ok. I'll word it for the v6: * Protocol 13 does not use PLLS, and NXP's RCWs for it power it down * (SRDS_PLL_PD_PLL2=1), which leaves PLLSRSTCTL[DIS] set: software can * clear it. > > PLLS then gets the values a board booted with > > protocol 20 reads back. > > This sentence doesn't make too much grammatical sense ok !, I'll reword it. > So SRDS_PRTCL_S1 does not influence the refclk that the PLL expects, > instead SRDS_PLL_REF_CLK_SEL_S1 does. I just checked the RM: for 40GE, the PLLS bit selects 156MHz (0) or 161MHz (1). NXP's protocol 20 QDS RCW and ours use 1. > Technically, the board does not *have* to feed PLLS a refclk > frequency. We have the SRDS_INTRA_REF_CLK_S1 option ok So, the code only needs 161MHz at PLLS, where it comes from does not matter. On nbxv3 both SD1 reference clock inputs are fed 161MHz, so I have not tested SRDS_INTRA_REF_CLK_S1. v6 names both sources. > Is this what you intend? It doesn't necessarily read as a conscious > decision. It is a conscious decision, but the comment did not say so. Only 161MHz is supported/checked, because it is the only one I can run. For 156MHz, PLLSCR0[REFCLK_SLE] would be 00010b, and I would also need the CR1/CR5 values the SoC loads for it, which I cannot check. It can be added later, by a board that handles it. v6 will state so, and also that the PLL lock bit does not prove the reference frequency: * Only a 161.1328125 MHz PLLS reference clock is supported. It comes * from the SD1 PLLS reference clock input, or from the PLLF one when * the RCW sets SRDS_INTRA_REF_CLK_S1=1, as 25GE and 100GE already need * 161.1328125 MHz on PLLF. 156.25 MHz, also valid for a 10.3125 GHz * clock net, would need PLLSCR0[REFCLK_SEL]=00010b and is not handled. * Nothing here can check the reference clock: PLLSRSTCTL[LOCK] does * not tell its frequency. Thanks, Vincent
