On 9/28/26 10:08 AM, Julien Stephan wrote:
> The display data path (ddp) is the set of muxes of the mmsys register
> space routing the components of the video pipeline into each other.
>
...
> +static void mtk_ddp_ovl_to_dsi_color_pipeline(void __iomem *mmsys_base)
> +{
> + /* OVL0 -> RDMA0 */
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
> + MT8365_OVL0_MOUT_PATH0_SEL, MT8365_DISP_MS_IN_OUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
> + MT8365_RDMA0_SEL_IN_OVL0, MT8365_DISP_MS_IN_OUT_MASK);
> +
> + /* RDMA0 -> COLOR0 */
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
> + MT8365_RDMA0_RSZ0_SEL_IN_RDMA0,
> MT8365_DISP_MS_IN_OUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
> + MT8365_RDMA0_SOUT_COLOR0, MT8365_DISP_MS_IN_OUT_MASK);
> +
> + /* COLOR0 -> CCORR0 -> AAL0 -> GAMMA0 -> DITHER0 -> DSI0 */
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
> + MT8365_DISP_COLOR_SEL_IN_COLOR0,
> MT8365_DISP_MS_IN_OUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> + MT8365_DITHER_MOUT_EN_DSI0, MT8365_DISP_MS_IN_OUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> + MT8365_DSI0_SEL_IN_DITHER, MT8365_DISP_MS_IN_OUT_MASK);
> +}
> +
> +static void mtk_ddp_ovl_to_dsi_crossbar(void __iomem *mmsys_base)
> +{
> + /* OVL0 -> RDMA0 */
> + mtk_ddp_mask(mmsys_base, MT8366_DISP_OVL0_BGCLR_MOUT_EN,
> + MT8366_MOUT_OVL_TO_BLENDOUT,
> MT8366_DISP_OVL_BGCLR_MOUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8366_DISP_OVL0_OUT0_MOUT_EN,
> + MT8366_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8366_DISP_OVL_OUT0_MOUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8366_DISP_RDMA0_SEL_IN,
> + MT8366_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT,
> + MT8366_DISP_RDMA_SEL_IN_MASK);
> +
> + /* RDMA0 -> COMP_OUT_CROSSBAR4 -> DSI0 */
> + mtk_ddp_mask(mmsys_base, MT8366_DISP_RDMA0_RSZ0_SOUT_SEL,
> + MT8366_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1,
> + MT8366_OVL_PQ_OUT_CROSSBAR_MOUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8366_OVL_PQ_OUT_CROSSBAR1_MOUT_EN,
> + MT8366_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4,
> + MT8366_OVL_PQ_OUT_CROSSBAR_MOUT_MASK);
> + mtk_ddp_mask(mmsys_base, MT8366_COMP_OUT_CROSSBAR4_MOUT_EN,
> + MT8366_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DSI0,
> + MT8366_COMP_OUT_CROSSBAR_MOUT_MASK);
> +}
> +
> +void mtk_ddp_ovl_to_dsi(void __iomem *mmsys_base, bool has_color_pipeline)
More on this in patch 11. Boolean isn't really enough here to cover all
possibilities.
> +{
> + if (has_color_pipeline)
> + mtk_ddp_ovl_to_dsi_color_pipeline(mmsys_base);
> + else
> + mtk_ddp_ovl_to_dsi_crossbar(mmsys_base);
> +}
