Add GCC_USB1 gate clocks, resets and the mock_utmi rate-set handler needed to bring up the USB1 (HS) controller on IPQ9650.
Signed-off-by: Badhrinath S <[email protected]> --- drivers/clk/qcom/clock-ipq9650.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/clk/qcom/clock-ipq9650.c b/drivers/clk/qcom/clock-ipq9650.c index 29c0c3fdf49f..52fd373625b1 100644 --- a/drivers/clk/qcom/clock-ipq9650.c +++ b/drivers/clk/qcom/clock-ipq9650.c @@ -20,6 +20,9 @@ #define GCC_IM_SLEEP_CBCR 0x1834020u +#define GCC_USB1_MOCK_UTMI_CMD_RCGR 0x3C004 +#define GCC_USB1_MOCK_UTMI_DIV_CDIVR 0x3C018 + static ulong ipq9650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -33,6 +36,12 @@ static ulong ipq9650_set_rate(struct clk *clk, ulong rate) clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg, 5, 0, 0, CFG_CLK_SRC_GPLL2_MAIN, 16); return rate; + case GCC_USB1_MOCK_UTMI_CLK: + /* Default: 24MHz */ + writel(0, priv->base + GCC_USB1_MOCK_UTMI_DIV_CDIVR); + clk_rcg_set_rate_mnd(priv->base, GCC_USB1_MOCK_UTMI_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_CXO, 8); + return rate; } return 0; } @@ -41,6 +50,11 @@ static const struct gate_clk ipq9650_clks[] = { GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x3303c, BIT(0), 0x3303c), GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x3302c, BIT(0), 0x33004), GATE_CLK_POLLED(GCC_QUPV3_WRAP_SE6_CLK, 0x04018, BIT(0), 0x04004), + GATE_CLK(GCC_USB1_PHY_CFG_AHB_CLK, 0x3C01C, BIT(0)), + GATE_CLK(GCC_USB1_SLEEP_CLK, 0x3C020, BIT(0)), + GATE_CLK(GCC_USB1_MOCK_UTMI_CLK, 0x3C024, BIT(0)), + GATE_CLK(GCC_USB1_MASTER_CLK, 0x3C028, BIT(0)), + GATE_CLK(GCC_SNOC_USB_CLK, 0x2E0C4, BIT(0)), }; static int ipq9650_enable(struct clk *clk) @@ -55,6 +69,9 @@ static int ipq9650_enable(struct clk *clk) static const struct qcom_reset_map ipq9650_gcc_resets[] = { [GCC_SDCC_BCR] = { 0x33000 }, + [GCC_USB_BCR] = { 0x2C000 }, + [GCC_USB1_BCR] = { 0x3C000 }, + [GCC_QUSB2_1_PHY_BCR] = { 0x3C030 }, }; static struct msm_clk_data ipq9650_gcc_data = { -- 2.34.1
